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| PRELIMINARY DATA SHEET MICRONAS MSP 3405D, MSP 3415D Multistandard Sound Processors Edition Oct. 14, 1999 6251-475-2PD MICRONAS MSP 34x5D Contents Page 5 5 5 5 5 6 6 6 6 7 7 7 10 10 10 11 11 12 12 12 12 12 12 12 13 13 13 13 13 14 14 15 16 17 18 18 18 18 18 19 Section 1. 1.1. 1.2. 1.3. 1.4. 2. 2.1. 2.2. 2.3. 3. 3.1. 3.2. 4. 4.1. 4.1.1. 4.1.2. 4.1.3. 4.1.4. 4.1.5. 4.1.6. 4.1.7. 4.1.8. 4.1.9. 4.1.10. 4.2. 4.2.1. 4.2.2. 4.3. 4.3.1. 4.4. 4.5. 4.6. 5. 5.1. 5.2. 5.2.1. 5.2.2. 5.2.3. 5.2.4. 5.3. Title PRELIMINARY DATA SHEET Introduction Common Features of MSP 34x5D Specific MSP 3415D Features Unsupported MSP 34x0D Functions MSP 34x0D Inputs and Outputs not included in the MSP 34x5D Basic Features of the MSP 34x5D Demodulator and NICAM Decoder Section DSP-Section (Audio Baseband Processing) Analog Section Application Fields of the MSP 34x5D NICAM plus FM/AM-Mono German 2-Carrier System (DUAL FM System) Architecture of the MSP 34x5D Demodulator and NICAM Decoder Section Analog Sound IF - Input Section Quadrature Mixers Low-pass Filtering Block for Mixed Sound IF Signals Phase and AM Discrimination Differentiators Low-pass Filter Block for Demodulated Signals High Deviation FM Mode FM-Carrier-Mute Function in the Dual Carrier FM Mode DQPSK-Decoder (MSP 3415D only) NICAM-Decoder (MSP 3415D only) Analog Section SCART Switching Facilities Stand-by Mode DSP-Section (Audio Baseband Processing) Dual Carrier FM Stereo/Bilingual Detection Audio PLL and Crystal Specifications Digital Control Output Pins I2S Bus Interface I2C Bus Interface: Device and Subaddresses Protocol Description Proposal for MSP 34x5D I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C-Controlling 2 Micronas PRELIMINARY DATA SHEET MSP 34x5D Contents, continued Page 20 20 21 21 22 22 23 24 24 26 27 29 29 30 31 31 31 31 32 32 32 32 32 34 34 34 34 34 36 36 37 38 38 39 39 40 40 40 41 41 41 42 42 43 43 43 Micronas Section 6. 6.1. 6.2. 6.3. 6.4. 6.4.1. 6.4.2. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.6. 6.6.1. 6.6.2. 6.6.3. 6.6.4. 6.6.5. 6.6.6. 6.6.7. 6.6.8. 6.6.9. 6.7. 6.8. 6.8.1. 6.8.2. 6.8.3. 6.8.4. 7. 7.1. 7.2. 7.3. 7.3.1. 7.3.2. 7.3.3. 7.3.4. 7.3.5. 7.3.6. 7.3.7. 7.3.8. 7.3.9. 7.3.10. 7.3.11. 7.3.12. 7.3.13. 7.3.14. Title Programming the Demodulator Section Short-Programming and General Programming of the Demodulator Part Demodulator Write Registers: Table and Addresses Demodulator Read Registers: Table and Addresses Demodulator Write Registers for Short-Programming: Functions and Values Demodulator Short-Programming AUTO_FM/AM: Automatic Switching between NICAM and FM/AM-Mono (MSP 3415D only) Demodulator Write Registers for the General Programming Mode: Functions and Values Register `AD_CV' Register `MODE_REG' FIR-Parameter DCO-Registers Demodulator Read Registers: Functions and Values Autodetect of Terrestrial TV-Audio Standards C_AD_BITS (MSP 3415D only) ADD_BITS [10...3] (MSP 3415D only) CIB_BITS (MSP 3415D only) ERROR_RATE (MSP 3415D only) CONC_CT (for compatibility with MSP 3410B) FAWCT_IST (for compatibility with MSP 3410B) PLL_CAPS AGC_GAIN Sequences to Transmit Parameters and to Start Processing Software Proposals for Multistandard TV-Sets Multistandard Including System B/G or I (NICAM/FM-Mono only) or SECAM L (NICAM/AM-Mono only) Multistandard Including System B/G with NICAM/FM-Mono and German DUAL FM Satellite Mode Automatic Search Function for FM-Carrier Detection Programming the DSP Section (Audio Baseband Processing) DSP Write Registers: Table and Addresses DSP Read Registers: Table and Addresses DSP Write Registers: Functions and Values Volume Loudspeaker Channel Balance Loudspeaker Channel Bass Loudspeaker Channel Treble Loudspeaker Channel Loudness Loudspeaker Channel Spatial Effects Loudspeaker Channel Volume SCART1 Channel Source Modes Channel Matrix Modes SCART Prescale FM/AM Prescale FM Matrix Modes FM Fixed Deemphasis FM Adaptive Deemphasis 3 MSP 34x5D Contents, continued Page 43 43 43 43 44 44 44 44 45 45 45 45 46 46 46 46 46 47 47 49 52 55 57 57 58 62 66 67 68 Section 7.3.15. 7.3.16. 7.3.17. 7.3.18. 7.3.19. 7.3.20. 7.3.21. 7.3.22. 7.4. 7.5. 7.5.1. 7.5.2. 7.5.3. 7.5.4. 7.5.5. 7.5.6. 7.5.7. 8. 8.1. 8.2. 8.3. 8.4. 8.5. 8.5.1. 8.5.2. 8.5.3. 9. 10. 11. Title NICAM Prescale (MSP 3415D only) NICAM Deemphasis (MSP 3415D only) I2S1 and I2S2 Prescale ACB Register Beeper Identification Mode FM DC Notch Automatic Volume Correction (AVC) Exclusions for the Audio Baseband Features DSP Read Registers: Functions and Values Stereo Detection Register Quasi-Peak Detector DC Level Register MSP Hardware Version Code MSP Major Revision Code MSP Product Code MSP ROM Version Code Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Application Circuit Appendix A: MSP 34x5D Version History Data Sheet History PRELIMINARY DATA SHEET 4 Micronas PRELIMINARY DATA SHEET MSP 34x5D - Bass, treble, volume, loudness, and spatial effects processing - Full SCART in/out matrix without restrictions - Improved FM-identification (as in MSPC) - Demodulator short programming - Autodetection for terrestrial TV-sound standards Multistandard Sound Processor Release Notes: The hardware description in this document is valid for the MSP 34x5D version A2 and following versions. Revision bars indicate significant changes to the previous edition. 1. Introduction The MSP 34x5D is designed as a single-chip Multistandard Sound Processor for applications in analog and digital TV sets, video recorders, and PC-cards. As derivative versions of the MSP 34x0D, the MSP 34x5D combines all demodulator features of the MSP 34x0D with less I/O and reduced audio baseband processing. The IC is produced in submicron CMOS technology, combined with high-performance digital signal processing. The MSP 34x5D is available in the following packages: PLCC68, PSDIP64, PSDIP52, PQFP80, and PMQFP44. Note: The MSP 34x5D version has reduced control registers and less functional pins. The remaining registers are software compatible to the MSP 3410D. The pinning is compatible to the MSP 3410D. - Improved carrier mute algorithm (as in MSPD) - Improved AM-demodulation (as in MSPD) - Digital control output pins D_CTR_OUT0/1 - Reduction of necessary controlling - Less external components 1.2. Specific MSP 3415D Features - All NICAM standards - Precise bit-error rate indication - Automatic switching from NICAM to FM/AM or vice versa - Improved NICAM synchronization algorithm 1.3. Unsupported MSP 34x0D Functions - Equalizer 1.1. Common Features of MSP 34x5D - Dolby Pro Logic together with DPL 351xA - Analog sound IF input - No external filters required - Stereo baseband input via integrated A/D converters - Two pairs of D/A converters - Two carrier FM - I2S Interface for version B3 and later versions 1.4. MSP 34x0D Inputs and Outputs not included in the MSP 34x5D - 2nd IF input - 3rd and 4th SCART input - 2nd SCART output - 2nd SCART DA - Headphone output - Subwoofer output - ADR interface - AVC: Automatic Volume Correction I2C 2 I2S 5 Sound IF 1 MONO IN SCART1 IN SCART2 IN 2 2 2 Loudspeaker OUT MSP 34x5D 2 SCART OUT Fig. 1-1: Main I/O signals of the MSP 34x5D Micronas 5 MSP 34x5D 2. Basic Features of the MSP 34x5D 2.1. Demodulator and NICAM Decoder Section The MSP 3415D is designed to simultaneously perform digital demodulation and decoding of NICAM-coded TV stereo sound, as well as demodulation of FM or AMmono TV sound. Alternatively, two carrier FM systems according to the German terrestrial specs can be processed with the MSP 34x5D. The MSP 34x5D facilitates profitable multistandard capability, offering the following advantages: - Automatic Gain Control (AGC) for analog input: input range: 0.10 - 3 Vpp - integrated A/D converter for sound IF input - all demodulation and filtering is performed on chip and is individually programmable - easy realization of all digital NICAM standards (B/G, I, L and D/K, not for MSP 3405D) - FM-demodulation of all terrestrial standards (including identification decoding) - no external filter hardware is required - only one crystal clock (18.432 MHz) is necessary - high deviation FM-mono mode (max. deviation: approx. 360 kHz) 2.2. DSP-Section (Audio Baseband Processing) - two digital inputs and one digital output via I2S bus for external signal processors like the DPL 351x. - flexible selection of audio sources to be processed - performance of terrestrial deemphasis systems (FM, NICAM) - digitally performed FM-identification decoding and dematrixing - digital baseband processing: volume, bass, treble, loudness, and spatial effects - simple controlling of volume, bass, treble, loudness, and spatial effects 2.3. Analog Section PRELIMINARY DATA SHEET - two selectable analog pairs of audio baseband inputs (= two SCART inputs) input level: 2 V RMS, input impedance: 25 k - one selectable analog mono input (i.e. AM sound): input level: 2 V RMS, input impedance: 15 k - two high-quality A/D converters, S/N-Ratio: 85 dB - 20 Hz to 20 kHz bandwidth for SCART-to-SCART-copy facilities - loudspeaker: one pair of four-fold oversampled D/A-converters output level per channel: max. 1.4 VRMS output resistance: max. 5 k S/N-ratio: 85 dB at maximum volume max. noise voltage in mute mode: 10 V (BW: 20 Hz ...16 kHz) - one pair of four-fold oversampled D/A converters supplying a pair of SCART-outputs. output level per channel: max. 2 V RMS, output resistance: max. 0.5 k, S/N-Ratio: 85 dB (20 Hz...16 kHz) 6 Micronas PRELIMINARY DATA SHEET MSP 34x5D In the case of NICAM/FM (AM) mode, there are three different audio channels available: NICAM A, NICAM B, and FM/AM-mono. NICAM A and B may belong either to a stereo or to a dual language transmission. Information about operation mode and about the quality of the NICAM signal can be read by the CCU via the control bus. In the case of low quality (high bit error rate), the CCU may decide to switch to the analog FM/AM-mono sound. Alternatively, an automatic NICAM-FM/AM switching may be applied. 3.2. German 2-Carrier System (DUAL FM System) Since September 1981, stereo and dual sound programs have been transmitted in Germany using the 2-carrier system. Sound transmission consists of the already existing first sound carrier and a second sound carrier additionally containing an identification signal. More details of this standard are given in Tables 3-1 and 3-4. For D/K and M-Korea, very similar systems are used. 3. Application Fields of the MSP 34x5D In the following sections, a brief overview about the two main TV sound standards, NICAM 728 and German FMStereo, demonstrates the complex requirements of a multistandard audio IC. 3.1. NICAM plus FM/AM-Mono According to the British, Scandinavian, Spanish, and French TV-standards, high-quality stereo sound is transmitted digitally. The systems allow two high-quality digital sound channels to be added to the already existing FM/AM-channel. The sound coding follows the format of the so-called Near Instantaneous Companding System (NICAM 728). Transmission is performed using Differential Quadrature Phase Shift Keying (DQPSK). Table 3-2 gives some specifications of the sound coding (NICAM); Table 3-3 offers an overview of the modulation parameters. Table 3-1: TV standards TV-System B/G B/G L I D/K Position of Sound Carrier [MHz] 5.5/5.7421875 5.5/5.85 6.5/5.85 6.0/6.552 6.5 /6.2578125 D/K1 6.5/6.7421875 D/K2 6.5/5.85 D/K-NICAM 4.5 4.5/4.724212 6.5 7.02/7.2 Sound Modulation FM-Stereo FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo FM-Mono/NICAM FM-Mono FM-Stereo FM-Mono FM-Stereo NTSC PAL PAL Color System PAL PAL SECAM-L PAL SECAM-East Country Germany Scandinavia,Spain France UK USSR Hungary USA Korea Europe (ASTRA) Europe (ASTRA) M M-Korea Satellite Satellite Micronas 7 MSP 34x5D Table 3-2: Summary of NICAM 728 sound coding characteristics Characteristics Audio sampling frequency Number of channels Initial resolution Companding characteristics Coding for compressed samples Preemphasis Audio overload level Values 32 kHz 2 14 bit/sample PRELIMINARY DATA SHEET near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks 2's complement CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz) +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz) Table 3-3: Summary of NICAM 728 sound modulation parameters Specification Carrier frequency of digital sound Transmission rate Type of modulation Spectrum shaping Roll-off Roll off factor 1.0 Carrier frequency of analog sound component 6.0 MHz FM mono 0.4 5.5 MHz FM mono I 6.552 MHz B/G 5.85 MHz L 5.85 MHz 728 kBit/s Differentially encoded quadrature phase shift keying (DQPSK) by means of Roll-off filters 0.4 6.5 MHz AM mono terrestrial Power ratio between vision carrier and analog sound carrier Power ratio between analog and modulated digital sound carrier 10 dB 13 dB 10 dB cable 16 dB 13 dB 0.4 6.5 MHz FM mono D/K 5.85 MHz 10 dB 7 dB 17 dB 11 dB Hungary 12 dB Poland 7 dB 8 Micronas PRELIMINARY DATA SHEET MSP 34x5D Table 3-4: Key parameters for B/G, D/K, and M 2-carrier sound system Sound Carriers B/G Vision/sound power difference Sound bandwidth Pre-emphasis Frequency deviation Sound Signal Components Mono transmission Stereo transmission Dual sound transmission mono (L+R)/2 language A (L+R)/2 R language B mono (L-R)/2 50 s 50 kHz Carrier FM1 D/K 13 dB 40 Hz to 15 kHz 75 s 25 kHz 50 s 50 kHz 75 s 25 kHz M B/G Carrier FM2 D/K 20 dB M Identification of Transmission Mode on Carrier FM2 Pilot carrier frequency in kHz Type of modulation Modulation depth Modulation frequency 54.6875 AM 50% mono: unmodulated stereo: 117.5 Hz dual: 274.1 Hz 149.9 Hz 276.0 Hz 55.0699 33 34 39 MHz 5 9 MHz According to the mixing characteristics of the Sound-IF mixer, the Sound-IF filter may be omitted. SAW Filter Sound IF Mixer Sound IF Filter Tuner Loudspeaker Vision Demodulator Mono 1 MSP 34x5D Composite Video SCART Inputs SCART1 SCART2 2 2 SCART1 SCART Output 2 I 2S1 Dolby Pro Logic Processor DPLA I 2S2 Digital Signal Source Fig. 3-1: Typical MSP 34x5D application Micronas 9 MSP 34x5D 4. Architecture of the MSP 34x5D Fig. 4-1 shows a simplified block diagram of the IC. Its architecture is split into three main functional blocks: 1. demodulator and NICAM decoder section 2. digital signal processing (DSP) section performing audio baseband processing 3. analog section containing two A/D-converters, four D/A-converters, and SCART switching facilities. PRELIMINARY DATA SHEET 4.1. Demodulator and NICAM Decoder Section 4.1.1. Analog Sound IF - Input Section The input pins ANA_IN1+ and ANA_IN- offer the possibility to connect sound IF (SIF) sources to the MSP 34x5D. The analog-to-digital conversion of the preselected sound IF signal is done by an A/D-converter, whose output can be used to control an analog automatic gain circuit (AGC), providing an optimal level for a wide range of input levels. It is possible to switch between automatic gain control and a fixed (setable) input gain. In the optimal case, the input range of the A/D converter is completely covered by the sound IF source. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, filtering is recommended. It was found, that the high pass filters formed by the coupling capacitors at pin ANA_IN1+ (as shown in the application diagram) are sufficient in most cases. I2S_CL I2S_DA_OUT I2S_WS I2S_DA_IN1 I2S_DA_IN2 XTAL_IN XTAL_OUT I2S Interface Audio PLL I2S1/2L/R I2S_L/R 2 D_CTR_OUT0/1 Sound IF ANA_IN1+ Demodulator and NICAM Decoder FM1/AM FM2 NICAM A NICAM B LOUDSPEAKER L LOUDSPEAKER R D/A D/A DACM_L Loudspeaker DACM_R IDENT Mono MONO_IN DSP SC1_IN_L SCART1 SC1_IN_R A/D A/D SCART L SCART1_L SCART R SCART1_R D/A D/A SC1_OUT_L SCART SC1_OUT_R SC2_IN_L SCART2 SC2_IN_R SCART Switching Facilities Fig. 4-1: Architecture of the MSP 34x5D 10 Micronas PRELIMINARY DATA SHEET MSP 34x5D 4.1.3. Low-pass Filtering Block for Mixed Sound IF Signals Data shaping and/or FM bandwidth limitation is performed by a linear phase Finite Impulse Response (FIRfilter). Just like the oscillators' frequency, the filter coefficients are programmable and are written into the IC by the CCU via the control bus. Thus, for example, different NICAM versions can easily be implemented. Two not necessarily different sets of coefficients are required, one for MSP-Ch1 (NICAM or FM2) and one for MSPCh2 (FM1 = FM-mono). In section 6.5.3., several coefficient sets are proposed. 4.1.2. Quadrature Mixers The digital input coming from the integrated A/D converter may contain audio information at a frequency range of theoretically 0 to 9 MHz corresponding to the selected standards. By means of two programmable quadrature mixers, two different audio sources; for example, NICAM and FM-mono, may be shifted into baseband position. In the following, the two main channels are provided to process either: - NICAM (MSP-Ch1) and FM/AM mono (MSP-Ch2) simultaneously or, alternatively, - FM2 (MSP-Ch1) and FM1 (MSP-Ch2). NICAM is not possible with MSP 3405D. Two programmable registers, to be divided up into low and high part, determine frequency of the oscillator, which corresponds to the frequency of the desired audio carrier. In section 6.2., format and values of the registers are listed. DCO1 MODE_REG[6] Oscillator FIR1 Phase Mixer VREFTOP Lowpass Phase and AM Discrimination Differentiator DQPSK Decoder NICAM Decoder NICAMA NICAMB MSP 3415D only Mute Lowpass FM2 MSP sound IF channel 1 (MSP-Ch1: FM2, NICAM) AD_CV[7:1] Amplitude Carrier Detect Mixer IDENT ANA_IN1+ AGC AD AD_CV[9] Carrier Detect ANA_IN- MSP sound IF channel 2 (MSP-Ch2: FM1, AM) Mixer Lowpass Amplitude Phase and AM Discrimination Phase Mute Differentiator Lowpass FM1/AM FRAME NICAMA DCO2 Pins Internal signal lines (see fig. 4-5) Demodulator Write Registers DCO2 Oscillator FIR2 MODE_REG[8] Fig. 4-2: Demodulator architecture of MSP 34x5D Micronas 11 MSP 34x5D 4.1.4. Phase and AM Discrimination The filtered sound IF signals are demodulated by means of the phase and amplitude discriminator block. On the output, the phase and amplitude is available for further processing. AM signals are derived from the amplitude information, whereas the phase information serves for FM and NICAM (DQPSK) demodulation. 4.1.5. Differentiators FM demodulation is completed by differentiating the phase information output. 4.1.6. Low-pass Filter Block for Demodulated Signals The demodulated FM and AM signals are further lowpass filtered and decimated to a final sampling frequency of 32 kHz. The usable bandwidth of the final baseband signals is about 15 kHz. 4.1.7. High Deviation FM Mode By means of MODE_REG [9], the maximum FM-deviation can be extended to approximately 360 kHz. Since this mode can be applied only for the MSP sound IF channel 2, the corresponding matrices in the baseband processing must be set to sound A. Apart from this, the coefficient sets 380 kHz FIR2 or 500 kHz FIR2 must be chosen for the FIR2. In relation to the normal FM-mode, the audio level of the high-deviation mode is reduced by 6 dB. The FM-prescaler should be adjusted accordingly. In high deviation FM-mode, neither FM-stereo nor FMidentification nor NICAM processing is possible simultaneously. PRELIMINARY DATA SHEET 4.1.8. FM-Carrier-Mute Function in the Dual Carrier FM Mode To prevent noise effects or FM identification problems in the absence of one of the two FM carriers, the MSP 3415 D offers a carrier detection feature, which must be activated by means of AD_CV[9]. If no FM carrier is available at the MSPD channel 1, the corresponding channel FM2 is muted. If no FM carrier is available at the MSPD channel 2, the corresponding channel FM1 is muted. 4.1.9. DQPSK-Decoder (MSP 3415D only) In case of NICAM-mode, the phase samples are decoded according the DQPSK-coding scheme. The output of this block contains the original NICAM-bitstream. 4.1.10. NICAM-Decoder (MSP 3415D only) Before any NICAM decoding can start, the MSP must lock to the NICAM frame structure by searching and synchronizing to the so-called Frame Alignment Words (FAW). To reconstruct the original digital sound samples, the NICAM-bitstream has to be descrambled, deinterleaved, and rescaled. Also, bit error detection and correction (concealment) is performed in this NICAM specific block. To facilitate the Central Control Unit CCU to switch the TV-set to the actual sound mode, control information on the NICAM mode and bit error rate are supplied by the the NICAM-Decoder. It can be read out via the I2C-Bus. An automatic switching facility (AUTO_FM) between NICAM and FM/AM reduces the amount of CCU-instructions in case of bad NICAM reception. 12 Micronas PRELIMINARY DATA SHEET MSP 34x5D 4.3. DSP-Section (Audio Baseband Processing) All audio baseband functions are performed by digital signal processing (DSP). The DSP functions are grouped into three processing parts: input preprocessing, channel source selection, and channel postprocessing (see Fig. 4-5 and section 7.). The input preprocessing is intended to prepare the various signals of all input sources in order to form a standardized signal at the input to the channel selector. The signals can be adjusted in volume, are processed with the appropriate deemphasis, and are dematrixed if necessary. Having prepared the signals that way, the channel selector makes it possible to distribute all possible source signals to the desired output channels. All input and output signals can be processed simultaneously with the exception that FM2 cannot be processed at the same time as NICAM. FM-identification and adaptive deemphasis are not possible simultaneously (if adaptive deemphasis is active, the ID-level in stereo detection register is not valid). 4.2. Analog Section 4.2.1. SCART Switching Facilities The analog input and output sections include full matrix switching facilities, which are shown in Fig. 4-3. The switches are controlled by the ACB bits defined in the audio processing interface (see section 7. Programming the DSP Section). SCART_IN SC1_IN_L/R SC2_IN_L/R to Audio Baseband Processing (DSP_IN) A D SCARTL/R ACB[5,9,8] MONO_IN S1 ACB[6,11,10] intern. signal lines pins from Audio Baseband Processing (DSP_OUT) SCART1_L/R D A SCART_OUT SC1_OUT_L/R 4.3.1. Dual Carrier FM Stereo/Bilingual Detection For the terrestrial dual FM carrier systems, audio information can be transmitted in three modes: mono, stereo, or bilingual. To obtain information about the current audio operation mode, the MSP 34x5D detects the socalled identification signal. Information is supplied via the Stereo Detection Register to an external CCU. S2 Fig. 4-3: SCART switching facilities (see 7.3.18.) Switching positions show the default configuration after power-on reset. Note: SCART_OUT is undefined after RESET! 4.2.2. Stand-by Mode If the MSP 34x5D is switched off by first pulling STANDBYQ low, and then disconnecting the 5 V, but keeping the 8 V power supply (`Stand-by'-mode), the switches S1 and S2 (see Fig. 4-3) maintain their position and function. This facilitates the copying from selected SCART-inputs to SCART-outputs in the TV-set's standby mode. In case of power-on start or starting from stand-by, the IC switches automatically to the default configuration, shown in Fig. 4-3. This action takes place after the first I2C transmission into the DSP part. By transmitting the ACB register first, the individual default setting mode of the TV set can be defined. Stereo Detection Filter IDENT AM Demodulation Bilingual Detection Filter Level Detect Stereo Detection Register - Level Detect Fig. 4-4: Stereo/bilingual detection Micronas 13 MSP 34x5D PRELIMINARY DATA SHEET Analog Inputs SCARTL SCARTR SCART Prescale Loudspeaker Channel Matrix AVC Bass Treble Volume Loudness Balance Loudspeaker L Loudspeaker Outputs Loudspeaker R DC level readout FM1 Beeper FM1/AM FM2 Demodulated IF Inputs NICAMA NICAMB MSP 3415D only Deemphasis 50/75 s FM /AM FM-Matrix Prescale DC level readout FM2 Channel Souce Select SCART1 Channel Matrix Volume SCART1_L SCART1_R SCART Output Deemphasis J17 NICAM Prescale Quasi peak readout L Quasi-Peak Detector Quasi peak readout R I 2S1L I 2S1R Bus nputs I 2S2L I 2S2R I 2S2 Prescale NICAMA Internal signal lines (see Fig. 4-2 and Fig. 4-3) 2S I 2S1 Prescale I 2SL I 2SR I 2S Channel Matrix I 2S Outputs Fig. 4-5: Audio Baseband Processing (DSP-Firmware) Table 4-1: Some examples for recommended channel assignments for demodulator and audio processing part Mode B/G-Stereo B/G-Bilingual NICAM-I-ST/ FM-mono Sat-Mono Sat-Stereo Sat-Bilingual Sat-High Dev. Mode MSP Sound IFChannel 1 FM2 (5.74 MHz): R FM2 (5.74 MHz): Sound B NICAM (6.552 MHz) not used 7.2 MHz: R 7.38 MHz: Sound C don't care MSP Sound IFChannel 2 FM1 (5.5 MHz): (L+R)/2 FM1 (5.5 MHz): Sound A FM (6.0 MHz): mono FM (6.5 MHz): mono 7.02 MHz: L 7.02 MHz: Sound A 6.552 MHz FMMatrix B/G Stereo No Matrix No Matrix No Matrix No Matrix No Matrix No Matrix ChannelSelect Speakers: FM Speakers: FM Speakers: NICAM Speakers: FM Speakers: FM Speakers: FM Speakers: FM Channel Matrix Stereo Speakers: Sound A H. Phone: Sound B Speakers: Stereo H. Phone: Sound A Sound A Stereo Speakers: Sound A H. Phone: Sound B=C Speakers: Sound A H. Phone: Sound A 4.4. Audio PLL and Crystal Specifications The MSP 34x5D requires a 18.432 MHz (12 pF, parallel) crystal. The clock supply of the whole system depends on the MSP 34x5D operation mode: 1. FM-Stereo, FM-Mono: The system clock runs free on the crystal's 18.432 MHz. 2. NICAM: An integrated clock PLL uses the 364 kHz baud-rate, accomplished in the NICAM demodulator block, to lock the system clock to the bit rate, respectively, 32 kHz sampling rate of the NICAM transmitter. As a re14 sult, the whole audio system is supplied with a controlled 18.432 MHz clock. Remark on using the crystal: External capacitors at each crystal pin to ground are required (see General Crystal Recommendations on page 60). 4.5. Digital Control Output Pins The static level of two output pins of the MSP 34x5D (D_CTR_OUT0/1) is switchable between HIGH and LOW by means of the I2C-bus. This enables the controlling of external hardware controlled switches or other devices via I2C-bus (see section 7.3.18.). Micronas PRELIMINARY DATA SHEET MSP 34x5D The I2S bus interface consists of five pins: 1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32 kHz) are transmitted. 2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. 3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz). 4. I2S_WS: The I2S_WS word strobe line defines the left and right sample. A precise I2S timing diagram is shown in Fig. 4-6. 4.6. I2S Bus Interface By means of this standardized interface, additional feature processors can be connected to the MSP 34x0D. Two possible formats are supported: The standard mode (MODE_REG[4]=0) selects the SONY format, where the I2S_WS signal changes at the word boundaries. The PHILIPS format, which is characterized by a change of the I2S_WS signal one I2S_CL period before the word boundaries, is selected by setting MODE_REG[4]=1. The MSP 34x5D normally serves as the master on the I2S interface. Here, the clock and word strobe lines are driven by the MSP. By setting MODE_REG[3]=1, the MSP 34x5D is switched to a slave mode. Now, these lines are input to the MSP and the master clock is synchronized to 576 times the I2S_WS rate (32 kHz). NICAM operation is not possible in this mode. (Data: MSB first) 1/FI2SWS I2S_WS SONY Mode PHILIPS Mode PHILIPS/SONY Mode programmable by MODE_REG[4] I2S_CL Detail A I2S_DAIN R LSB L MSB SONY Mode PHILIPS Mode Detail C L LSB R MSB R LSB L LSB 16 bit left channel Detail B I2S_DAOUT R LSB L MSB L LSB R MSB 16 bit right channel R LSB L LSB 16 bit left channel 16 bit right channel Detail C I2S_CL 1/FI2SCL Detail A,B I2S_CL TI2SWS1 TI2SWS2 TI2S1 TI2S2 I2S_WS as INPUT TI2S5 TI2S6 I2S_DA_IN TI2S3 TI2S4 I2S_WS as OUTPUT I2S_DA_OUT Fig. 4-6: I2S bus timing diagram Micronas 15 MSP 34x5D 5. I2C Bus Interface: Device and Subaddresses As a slave receiver, the MSP 34x5D can be controlled via I2C bus. Access to internal memory locations is achieved by subaddressing. The demodulator and the DSP processor parts have two separate subaddressing register banks. In order to allow for more MSP 34x5D ICs to be connected to the control bus, an ADR_SEL pin has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 34x5D responds to changed device addresses. Thus, three identical devices can be selected. By means of the RESET bit in the CONTROL register, all devices with the same device address are reset. The IC is selected by asserting a special device address in the address part of an I2C transmission. A device address pair is defined as a write address (80, 84, or 88hex) and a read address (81, 85, or 89hex) (see Table 5-1). Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the device write address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address (81, 85, or 89hex) and reading two bytes of data (see Fig. 5-1: "I2C Bus Protocol" and section 5.2. "Proposal for MSP 34x5D I2C Telegrams"). PRELIMINARY DATA SHEET Due to the internal architecture of the MSP 34x5D the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms for the DSP processor part and 1 ms for the demodulator part if NICAM processing is active. If the receiver (MSP) can't receive another complete byte of data until it has performed some other function; for example, servicing an internal interrupt, it can hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by 'Wait' in section 5.1. The maximum Wait-period of the MSP during normal operation mode is less than 1 ms. I2C bus error caused by MSP hardware problems: In case of any internal error, the MSPs wait-period is extended to 1.8 ms. Afterwards, the MSP does not acknowledge (NAK) the device address. The data line will be left HIGH by the MSP and the clock line will be released. The master can then generate a STOP condition to abort the transfer. By means of NAK, the master is able to recognize the error state and to reset the IC via I2C bus. While transmitting the reset protocol (see section 5.2.4. on page 18) to `CONTROL', the master must ignore the not acknowledge bits (NAK) of the MSP. A general timing diagram of the I2C bus is shown in Fig. 5-2 on page 18. Table 5-1: I2C Bus Device Addresses ADR_SEL Mode MSP device address Write 80hex Low Read 81hex Write 84hex High Read 85hex Write 88hex Left Open Read 89hex Table 5-2: I2C Bus Subaddresses Name CONTROL TEST WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0000 0001 0001 0000 0001 0001 0001 0010 0001 0011 Hex Value 00 01 10 11 12 13 Mode W W W W W W Function software reset only for internal use write address demodulator read address demodulator write address DSP read address DSP 16 Micronas PRELIMINARY DATA SHEET MSP 34x5D Table 5-3: Control Register (Subaddress: 00hex) Name CONTROL Subaddress 00 hex MSB 1 : RESET 0 : normal 14 0 13..1 0 LSB 0 5.1. Protocol Description Write to DSP or Demodulator S write device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK data-byte high ACK data-byte low ACK P Read from DSP or Demodulator S write device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK S read device address Wait ACK data-byte high Write to Control or Test Registers S write device address Wait ACK sub-addr ACK data-byte high ACK data-byte low ACK P Note: S = P= ACK = NAK = Wait = I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, gray) or master (= CCU, hatched) Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate `End of Read' or from MSP indicating internal error state I2C-Clock line held low by the slave (= MSP) while interrupt is serviced (<1.8 ms) I2C_DA S I2C_CL Fig. 5-1: I2C bus protocol 1 0 P (MSB first; data must be stable while clock is high) Micronas CC CC CCC CCC CC CCC ACK data-byte low NAK P 17 MSP 34x5D PRELIMINARY DATA SHEET 1/fI2C I2C_CL TI2C4 TI2C3 TI2C1 I2C_DA as input TI2C5 TI2C6 TI2C2 Data: MSB first TI2COL2 I2C_DA as output TI2COL1 Fig. 5-2: I2C bus timing diagram 5.2. Proposal for MSP 34x5D I2C Telegrams 5.2.1. Symbols daw dar < > aa dd write device address read device address Start Condition Stop Condition Address Byte Data Byte 5.2.2. Write Telegrams 18 Micronas PRELIMINARY DATA SHEET MSP 34x5D 5.3. Start-Up Sequence: Power-Up and I2C-Controlling After power-on or RESET (see Fig. 5-3), the IC is in an inactive state. The CCU has to transmit the required coefficient set for a given operation via the I2C bus. Initialization should start with the demodulator part. If required for any reason, the audio processing part can be loaded before the demodulator part. DVSUP AVSUP 4.5 V t/ms RESETQ 0.7 x DVSUP 0.45...0.55x DVSUP Low-to-High Threshold High-to-Low Threshold t/ms Reset Delay >2 ms Internal Reset High Low t/ms Power-up reset: threshold and timing Note: 0.7 x DVSUP means 3.5 Volt with DVSUP = 5.0 Volt Fig. 5-3: Power-up sequence Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms Micronas 19 MSP 34x5D 6. Programming the Demodulator Section 6.1. Short-Programming and General Programming of the Demodulator Part PRELIMINARY DATA SHEET The Demodulator Part of the MSP 34x5D can be programmed in two different modes: 1. Demodulator Short-Programming facilitates a comfortable way to set up the demodulator for many terrestrial TV-sound standards with one single I2C-Bus transmission. The coding is listed in section 6.4.1.. If a parameter doesn't coincide with the individual programming concept, it simply can be overwritten by using the General Programming mode. Some bits of the registers AD_CV (see section 6.5.1. ) and MODE_REG (see section 6.5.2. ) are not affected by the short-programming. They must be transmitted once if their reset status does not fit. The Demodulator Short-Programming is not compatible to MSP 3410B and MSP 3400C. Autodetection for terrestrial TV standards (as part of the below Demodulator Short-Programming) provides the most comfortable way to set up the MSPD-demodulator. This feature facilitates within 0.5 s the detection and set-up of the actual TV-sound standard. Since the detected standard is readable by the control processor, the autodetection feature is mainly recommended for the primary set-up of a TV-set: after having determined once the corresponding TV-channels, their sound standards can be stored and later on programmed by the Demodulator Short-Programming (see sections 6.4.1. and 6.6.1.). 2. General Programming ensures the software compatibility to other MSPs. It offers a very flexible way to apply all of the MSP 34x5D demodulator facilities. All registers except 0020hex have to be written with values corresponding to the individual requirements. For satellite applications, with their many variations, this mode must be selected. All transmissions on the control bus are 16 bits wide. However, data for the demodulator part have only 8 or 12 significant bits. These data have to be inserted LSBbound and filled with zero bits into the 16-bit transmission word. Table 4-1 explains how to assign FM carriers to the MSP-Sound IF channels and the corresponding matrix modes in the audio processing part. 20 Micronas PRELIMINARY DATA SHEET MSP 34x5D 6.2. Demodulator Write Registers: Table and Addresses Table 6-1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable! Demodulator Write Registers Demodulator ShortProgramming AUTO_FM/AM Address (hex) 0020 Function Write into this register to apply Demodulator Short Programming (see section 6.4.1.). If the internal setting coincidences with the individual requirements no more of the remaining Demodulator Write Registers have to be transferred. Only for NICAM (MSP 3415D): Automatic switching between NICAM and FM/AM in case of bad NICAM reception (see section 6.4.2.) 0021 Write Registers necessary for General Programming Mode only AD_CV MODE_REG FIR1 FIR2 DCO1_LO DCO1_HI DCO2_LO DCO2_HI PLL_CAPS 00BB 0083 0001 0005 0093 009B 00A3 00AB 001F input selection, configuration of AGC, Mute Function and selection of A/D-converter, FM-Carrier-Mute on/off mode register filter coefficients channel 1 (6 8 bit) filter coefficients channel 2 (6 8 bit), + 3 8 bit offset (total 72 bit) increment channel 1 Low Part increment channel 1 High Part increment channel 2 Low Part increment channel 2 High Part switchable PLL capacitors to tune open-loop frequency; to use only if NICAM of MODE_REG = 0 normally not of interest for the customer 6.3. Demodulator Read Registers: Table and Addresses Table 6-2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writeable! Demodulator Read Registers Result of Autodetection C_AD_BITS ADD_BITS CIB_BITS ERROR_RATE CONC_CT FAWCT_IST PLL_CAPS AGC_GAIN Address (hex) 007E 0023 0038 003E 0057 0058 0025 021F 021E Function see Table 6-13 NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits NICAM: bit [10:3] of additional data bits NICAM: CIB1 and CIB2 control bits NICAM error rate, updated with 182 ms only to be used in MSPB compatibility mode only to be used in MSPB compatibility mode Not for customer use. Not for customer use. Note: All NICAM relevant registers are "0" for MSP 3405D. Micronas 21 MSP 34x5D PRELIMINARY DATA SHEET 6.4. Demodulator Write Registers for Short-Programming: Functions and Values In the following, the functions of some registers are explained and their (default) values are defined: 6.4.1. Demodulator Short-Programming Table 6-3: MSP 34x5D Demodulator Short-Programming Demodulator Short-Programming TV-Sound Standard Description Code (hex) AD_CV2) (see Table 6-5) 0020hex Internal Setting MODE_ REG2) (see Table 6-8) DCO1 (MHz) DCO2 (MHz) FIR1/2 Coefficients Identification Mode Autodetection M Dual-FM B/G Dual-FM D/K1 Dual-FM D/K2 Dual-FM 0001 0002 0003 0004 0005 0006/ 0007 Detects and sets one of the standards listed below, if available. Results are to be read out of the demodulator read register "Result of Autodetection" (Section 6.6.1.) AD_CV-FM AD_CV-FM AD_CV-FM AD_CV-FM M1 M1 M1 M1 4.72421 5.74218 6.25781 6.74218 4.5 5.5 6.5 6.5 AUTO_ FM/AM see Table 6-11: Terrestrial TVStandards Reset, then Standard M Reset, Reset then Standard B/G reserved for future Dual FM Standards NICAM-Modes for MSP 3415D only; MSP 3405D responds with FM/AM Mono B/G-NICAM-FM L-NICAM-AM I-NICAM-FM D/K-NICAM-FM 0008 0009 000A 000B >000B 1) 2) AD_CV-FM AD_CV-AM AD_CV-FM AD_CV-FM M2 M3 M2 M2 5.85 5.85 6.552 5.85 5.5 6.5 6.0 6.5 see Table 6-11: Terrestrial TVTV Standards 1) reserved for future NICAM Standards corresponds to the actual setting of AUTO_FM (Address = 0021hex) Bits of AD_CV or MODE_REG, which are not affected by the short-programming, must be transmitted separately if their reset status does not fit. Note: All parameters in the DSP section (Audio Baseband Processing), except the identification mode register, are not affected by the Demodulator Short-Programming . They still have to be defined by the control processor. 22 Micronas PRELIMINARY DATA SHEET MSP 34x5D There are two possibilities to define the threshold deciding for NICAM or FM/AM-mono (see Table 6-4): 1. default value of the MSPD (internal threshold=700, i.e. switch to FM/AM if ERROR_RATE > 700) 2. definable by the customer (recommendable range: threshold = 50....2000, i. e. Bits [10:1] = 25...1000). Note: The auto_fm feature is only active if the NICAM-bit of MODE_REG is set. 6.4.2. AUTO_FM/AM: Automatic Switching between NICAM and FM/AM-Mono (MSP 3415D only) In case of bad NICAM transmission or loss of the NICAM-carrier, the MSPD offers a comfortable mode to switch back to the FM/AM-mono signal. If automatic switching is active, the MSP internally evaluates the ERROR_RATE. All output channels which are assigned to the NICAM-source are switched back to the FM/AMmono source without any further CCU instruction, if the NICAM-carrier fails or the ERROR_RATE exceeds the definable threshold. Note, that the channel matrix of the corresponding output-channels must be set according to the NICAM-mode and need not be changed in the FM/AM-fall-back case. An appropriate hysteresis algorithm avoids oscillating effects. Bit 11 of the register C_AD_BITS (Address: 0023hex) informs about the actual NICAM-FM/AM-Status (see section 6.6.2.). Table 6-4: Coding of automatic NICAM-FM/AM switching; reset status: mode 0 Mode 0. default 1. Auto_fm [11....0] Addr. = 0021hex Bit [0] =0 Bits [11...1] = 0 Bit [0] =1 Bit [11:1] = 0 Bit [0] =1 Bit [10:1] = 25...1000 int = threshold/2 Bit [11] =0 Bit [11] = [0] = 1 Bit [10...1]= 0 Selected Sound at the NICAM Channel Select always NICAM Threshold none Comment Compatible to MSP 3410B, i.e. automatic switching is disabled automatic switching with internal threshold automatic switching with external threshold NICAM or FM/AM, depending on ERROR_RATE NICAM or FM/AM, depending on ERROR_RATE always FM/AM 700 dec 2. set by customer 3. none Forced FM-mono mode, i.e. automatic switching is disabled Micronas 23 MSP 34x5D PRELIMINARY DATA SHEET 6.5. Demodulator Write Registers for the General Programming Mode: Functions and Values 6.5.1. Register `AD_CV' Table 6-5: AD_CV Register; reset status: all bits are "0" AD_CV 00BBhex Bit AD_CV [0] AD_CV [6:1] Meaning not used Reference level in case of Automatic Gain Control = on (see Table 6-6). Constant gain factor when Automatic Gain Control = off (see Table 6-7). Determination of Automatic Gain or Constant Gain not used MSP-Carrier-Mute Function (Must be switched off in High Deviation Mode) not used 0 = constant gain 1 = automatic gain must be set to 0 0 = off: no mute 1 = on: mute as described in section 4.1.8. on page 12 must be set to 0 Settings must be set to 0 Set by Short-Programming AD_CV-FM 0 101000 AD_CV-AM 0 100011 AD_CV [7] AD_CV [8] AD_CV [9] 1 not affected 1 1 not affected 0 AD_CV [15-10] 0 0 Table 6-6: Reference values for active AGC (AD_CV[7] = 1) Application Input Signal Contains AD_CV [6:1] Ref. Value AD_CV [6:1] in integer Range of Input Signal at pin ANA_IN1+ and ANA_IN2+ Terrestrial TV FM-Stereo FM/NICAM AM/NICAM 2 FM Carriers 1 FM and 1 NICAM Carrier 1 AM and 1 NICAM carrier 101000 101000 100011 40 40 35 0.10 - 3 Vpp1) 0.10 - 3 Vpp1) 0.10 - 1.4 Vpp recommended: 0.10 - 0.8Vpp 0.05 - 1.0 Vpp 0.10 - 3 Vpp1) NICAM only SAT 1 NICAM Carrier only 1 or more FM Carriers 010100 100011 20 35 1) For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may appear. 24 Micronas PRELIMINARY DATA SHEET MSP 34x5D Table 6-7: AD_CV parameters for constant input gain (AD_CV[7]=0) Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AD_CV [6:1] Constant Gain 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 Gain (dB) 3.00 3.85 4.70 5.55 6.40 7.25 8.10 8.95 9.80 10.65 11.50 12.35 13.20 14.05 14.90 15.75 16.60 17.45 18.30 19.15 20.00 maximum input level: 0.14 Vpp Input Level at pin ANA_IN1+ maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)1) 1) For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may appear. Micronas 25 MSP 34x5D 6.5.2. Register `MODE_REG' The register `MODE_REG' contains the control bits determining the operation mode of the MSP 34x5D; Table 6-8 explains all bit positions. PRELIMINARY DATA SHEET Table 6-8: Control word `MODE_REG'; reset status: all bits are "0" MODE_REG 0083hex Bit [0] [1] [2] Function not used DCTR_TRI I2S_TRI Digital Control Outputs active / tri-state I2S Outputs (I2S_CL, I2S_WS, I2S_DA_OUT) active / tri-state Master / Slave Mode of the I2S Bus WS due to the Sony or Philips format Comment Definition 0 : strongly recommended 0 : active 1 : tri-state 0 : active 1 : tri-state 0 : Master 1 : Slave 0 : Sony 1 : Philips 1 : recommended Mode of MSP-Ch1 MSP 3405D: always FM 0 : FM 1 : Nicam 0 : strongly recommended Mode of MSP-Ch2 High Deviation Mode (channel matrix must be sound A) 0 : FM 1 : AM 0 : normal 1 : high deviation mode 0 : strongly recommended see Table 6-11 see Table 6-11 0 : Gain = 6 dB 1 : Gain = 0 dB 0 : use FIR1 1 : use FIR2 0 : strongly recommended Gain for AM Demodulation 0 : 0 dB (default. of MSPB) 1 : 12 dB (recommended) Set by Short-Programming M1 0 X X M2 0 X X M3 0 X X [3] [4] [5] [6] [7] [8] [9] I2S Mode1) I2S_WS Mode not used NICAM 1) not used FM AM HDEV X X X 0 0 0 0 X X X 1 0 0 0 X X X 1 0 1 0 [11:10] [12] [13] [14] [15] 1) not used MSP-Ch1 Gain FIR1-Filter Coeff. Set not used AM-Gain 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 In case of NICAM operation, I2S slave mode is not possible. In case of I2S slave mode, no synchronization to NICAM is allowed. X: not affected by short-programming 26 Micronas PRELIMINARY DATA SHEET MSP 34x5D Table 6-9: Channel modes `MODE_REG [6, 8, 9]` NICAM bit[6] 1 1 0 0 FM AM bit[8] 0 1 0 0 HDEV bit[9] 0 0 0 1 FM2 - MSP-Ch1 NICAM (undefined sound for MSP 3405D) MSP-Ch2 FM1 AM FM1 High Deviation FM 6.5.3. FIR-Parameter The following data values (see Table 6-10) are to be transferred 8 bits at a time embedded LSB-bound in a 16-bit word. The loading sequences must be obeyed. To change a coefficient set, the complete block FIR1 or FIR2 must be transmitted. Note: For compatibility with MSP 3410B, IMREG1 and IMREG2 have to be transmitted. The value for IMREG1 and IMREG2 is 004. Due to the partitioning to 8-bit units, the values 04hex, 40hex, and 00hex arise. Table 6-10: Loading sequence for FIR-coefficients FIR1 0001hex No. 1 2 3 4 5 6 (MSP-Ch1: NICAM/FM2) Bits 8 8 8 see Table 6-11 6 11 NICAM/FM2_Coeff. (2) NICAM/FM2_Coeff. (1) NICAM/FM2_Coeff. (0) 8 8 8 Value Symbol Name NICAM/FM2_Coeff. (5) NICAM/FM2_Coeff. (4) NICAM/FM2_Coeff. (3) FIR2 0005hex No. 1 2 3 4 5 6 7 8 9 (MSP-Ch2: FM1/AM ) Bits 8 8 8 8 8 8 see Table 6-11 6 11 8 8 8 Value 04hex 40hex 00hex Symbol Name IMREG1 IMREG1 / IMREG2 IMREG2 FM/AM_Coef (5) FM/AM_Coef (4) FM/AM_Coef (3) FM/AM_Coef (2) FM/AM_Coef (1) FM/AM_Coef (0) Micronas 27 MSP 34x5D PRELIMINARY DATA SHEET Table 6-11: 8-bit FIR-coefficients (decimal integer) for MSP 34x5D; reset status: all coefficients are "0" Coefficients for FIR1 0001hex and FIR2 0005hex FM - Satellite FIR filter corresponds to a bandpass with a bandwidth of B = 130 to 500 kHz Terrestrial TV-Standards B fc frequency Autosearch FIR2 -1 -1 -8 2 59 126 0 B/G-, D/KNICAM-FM Coef(i) 0 1 2 3 4 5 MODEREG[12] MODEREG[13] FIR1 -2 -8 -10 10 50 86 0 FIR2 3 18 27 48 66 72 INICAM-FM FIR1 2 4 -6 -4 40 94 0 FIR2 3 18 27 48 66 72 LNICAM-AM FIR1 -2 -8 -10 10 50 86 0 FIR2 -4 -12 -9 23 79 126 B/G-,D/K-, M-Dual FM FIR2 3 18 27 48 66 72 0 130 kHz FIR2 73 53 64 119 101 127 1 180 kHz FIR2 9 18 28 47 55 64 1 200 kHz FIR2 3 18 27 48 66 72 1 280 kHz FIR2 -8 -8 4 36 78 107 1 380 kHz FIR2 -1 -9 -16 5 65 123 1 500 kHz FIR2 -1 -1 -8 2 59 126 1 0 0 0 1 1 1 1 1 1 1 0 For compatibility, except for the FIR2-AM and the autosearch sets, the FIR-filter programming as used for the MSP 3410B is also possible. 28 Micronas PRELIMINARY DATA SHEET MSP 34x5D 6.6. Demodulator Read Registers: Functions and Values All registers except C_AD_BITs are 8 bit wide. They can be read out of the RAM of the MSP 34x5D. All transmissions take place in 16-bit words. The valid 8 bit data are the 8 LSBs of the received data word. To enable appropriate switching of the channel select matrix of the baseband processing part, the NICAM or FM-identification parameters must be read and evaluated by the CCU. The FM-identification registers are described in section 7.2. To handle the NICAM-sound and to observe the NICAM-quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the CCU. Additional data bits and CIB bits, if supplied by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS. Observing the presence and quality of NICAM can be delegated to the MSP 34x5D, if the automatic switching feature (AUTO_FM, section 6.4.2.) is applied. 6.5.4. DCO-Registers For a chosen TV standard, a corresponding set of 24-bit registers determining the mixing frequencies of the quadrature mixers, has to be written into the IC. In Table 6-12, some examples of DCO registers are listed. It is necessary to divide them up into low part and high part. The formula for the calculation of the registers for any chosen IF-Frequency is as follows: INCRdec = int ( f / fs 224) with: int f fS = integer function = IF-frequency in MHz = sampling frequency (18.432 MHz) Conversion of INCR into hex-format and separation of the 12-bit low and high parts lead to the required register values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI or LO for MSP-Ch2). Table 6-12: DCO registers for the MSP 34x5D; reset status: DCO_HI/LO = "0000" DCO1_LO 0093hex, DCO1_HI 009Bhex; DCO2_LO 00A3hex, DCO2_HI 00ABhex Freq. [MHz] 4.5 5.04 5.5 5.58 5.7421875 6.0 6.2 6.5 6.552 7.02 7.38 DCO_HIhex 03E8 0460 04C6 04D8 04FC 0535 0561 05A4 05B0 0618 0668 DCO_LOhex 000 0000 038E 0000 00AA 0555 0C71 071C 0000 0000 0000 5.76 5.85 5.94 6.6 6.65 6.8 7.2 7.56 0500 0514 0528 05BA 05C5 05E7 0640 0690 0000 0000 0000 0AAA 0C71 01C7 0000 0000 Freq. [MHz] DCO_HIhex DCO_LOhex Micronas 29 MSP 34x5D 6.6.1. Autodetect of Terrestrial TV-Audio Standards By means of autodetect, the MSP 34x5D offers a simple and fast (<0.5 s) facility to detect the actual TV-audio standard. The algorithm checks for the FM-mono and NICAM carriers of all common TV-Sound Standards. The following notes must be considered when applying the autodetect feature: 1. Since there is no way to distinguish between AM and FM-carrier, a carrier detected at 6.5 MHz is interpreted as an AM-carrier. If video detection results in SECAM-East, the MSPD result "9" of autodetect must be reinterpreted as "Bhex" in case of CAD_BITS[0] = 1, or as "4" or "5" by using the demodulator short programming mode. A simple decision can be made between the two D/K FM-stereo standards by setting D/K1 and D/K2 using the short programming mode and checking the identification of both versions (see Table 6-13). PRELIMINARY DATA SHEET 2. During active autodetect, I2C-transfers are not recommended except for reading the autodetect result. Under no circumstances should the following parameters: Prescale FM/AM, FM Matrix, Deemphasis FM, Quasi-Peak Detector Source, and Quasi-Peak Detector Matrix be written. Results exceeding 07FFhex indicate an active autodetect. 3. The results are to be understood as static information, i.e. no evaluation of FM or NICAM identification concerning the dynamic mode (stereo, bilingual, or mono) are done. 4. Before switching to autodetect, the audio processing part should be muted. Do not forget to demute after having received the result. Table 6-13: Result of Autodetection Result of Autodetect Code (Data) hex >07FF 0000 0002 0003 0008 007Ehex Detected TV-Sound Standard Note: After detection the detected standard is set automatically according to Table 6-3. autodetect still active no TV Sound Standard was detected; select sound standard manually M Dual-FM, even if only FM1 is available B/G Dual-FM, even if only FM1 is available B/G-FM-NICAM, only if NICAM is available (MSP 3415D only) L_AM-NICAM, whenever a 6.5 MHz carrier is detected, even if NICAM is not available. If also D/K might be possible a decision has to be made according to the video-mode: Video = SECAM_EAST 0009 CAD_BITS[0] = 0 Video = SECAM_L no more activities necessary CAD_BITS[0] = 1 To be set by means of the short programming mode: D/K1 or D/K2 see section 6.6.1. D/K-NICAM (standard 000Bhex) 000A I-FM-NICAM, even if NICAM is not available Note: Similar as for the Demodulator Short-Programming, the Autodetection does not affect most of the parameters of the DSP section (Audio Baseband Processing): The following exceptions are to be considered: - identification mode: Autodetection resets and sets the corresponding identification mode. - Prescale FM/AM and FM matrix and Deemphasis FM are undefined after Autodetection. 30 Micronas PRELIMINARY DATA SHEET MSP 34x5D 6.6.3. ADD_BITS [10...3] (MSP 3415D only) Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system. Format: MSB 7 A[10] 6 A[9] 5 A[8] ADD_BITS 0038hex 4 A[7] 3 A[6] 2 A[5] 1 A[4] LSB 0 A[3] 6.6.2. C_AD_BITS (MSP 3415D only) NICAM operation mode control bits and A[2...0] of the additional data bits. Format: MSB 11 Auto _FM ... ... 7 A[2] C_AD_BITS 0023hex 6 A[1] 5 A[0] 4 C4 3 C3 2 C2 1 C1 LSB 0 S Important: "S" = Bit [0] indicates correct NICAM-synchronization (S=1). If S = 0, the MSP 34x5D has not yet synchronized correctly to frame and sequence, or has lost synchronization. The remaining read registers are therefore not valid. The MSP 34x5D mutes the NICAM output automatically and tries to synchronize again as long as MODE_REG[6] is set. The operation mode is coded by C4-C1 as shown in Table 6-14. Table 6-14: NICAM operation modes as defined by the EBU NICAM 728 specification C4 0 0 0 0 1 1 1 C3 0 0 0 0 0 0 0 C2 0 0 1 1 0 0 1 C1 0 1 0 1 0 1 0 Operation Mode Stereo sound (NICAMA/B), independent mono sound (FM1) Two independent mono signals (NICAMA, FM1) Three independent mono channels (NICAMA, NICAMB, FM1) Data transmission only; no audio Stereo sound (NICAMA/B), FM1 carries same channel One mono signal (NICAMA). FM1 carries same channel as NICAMA Two independent mono channels (NICAMA, NICAMB). FM1 carries same channel as NICAMA Data transmission only; no audio Unimplemented sound coding option (not yet defined by EBU NICAM 728 specification) 6.6.4. CIB_BITS (MSP 3415D only) Cib bits 1 and 2 (see NICAM 728 specifications) Format: MSB 7 x 6 x 5 x CIB_BITS 003Ehex 4 x 3 x 2 x 1 CIB1 LSB 0 CIB2 6.6.5. ERROR_RATE (MSP 3415D only) Average error rate of the NICAM reception in a time interval of 182 ms, which should be close to 0.. The initial and maximum value of ERROR_RATE is 2047. This value is also active, if the NICAM bit of MODE_REG is not set. Since the value is achieved by filtering, a certain transition time (appr. 0.5 sec) is unavoidable. Acceptable audio may have error_rates up to a value of 700int. Individual evaluation of this value by the CCU and an appropriate threshold may define the fallback mode from NICAM to FM/AM-mono in case of poor NICAM reception. The bit error rate per second (BER) can be calculated by means of the following formula: BER = ERROR_RATE * 12.3*10-6 /s If the automatic switching feature (AUTO_FM; section 6.4.2. on page 23) is applied, reading of ERROR_RATE can be omitted. ERROR_RATE Error free maximum error rate 0057hex 0000hex 07FFhex 1 x 0 1 1 x 1 x AUTO_FM: monitor bit for the AUTO_FM Status: 0: NICAM source is NICAM 1: NICAM source is FM Micronas 31 MSP 34x5D 6.6.6. CONC_CT (for compatibility with MSP 3410B) This register contains the actual number of bit errors of the previous 728-bit data frame. Evaluation of CONC_CT is no longer recommended. 6.6.7. FAWCT_IST (for compatibility with MSP3410B) For compatibility with MSP 3410B this value equals 12 as long as NICAM quality is sufficient. It decreases to 0 if NICAM reception gets poor. Evaluation of FAWCT_IST is no longer recommended. 6.6.8. PLL_CAPS It is possible to read out the actual setting of the PLL_CAPS. In standard applications, this register is not of interest for the customer. PLL_CAPS minimum frequency nominal frequency maximum frequency 0021Fhex 0111 1111 0101 0110 RESET 0000 0000 7Fhex 56hex 00hex PRELIMINARY DATA SHEET 6.7. Sequences to Transmit Parameters and to Start Processing After having been switched on, the MSP has to be initialized by transmitting the parameters according to the LOAD_SEQ_1/2 of Table 6-15. The data are immediately active after transmission into the MSP. It is no longer necessary to transmit LOAD_REG_1/2 or LOAD_REG_1 as it was for MSP 3410B. Nevertheless, transmission of LOAD_REG_1/2 or LOAD_REG_1 does no harm. For NICAM operation, the following steps listed in `NICAM_WAIT, _READ and _Check' in Table 6-15 must be taken. For FM-stereo operation, the evaluation of the identification signal must be performed. For a positive identification check, the MSP 34x5D sound channels have to be switched corresponding to the detected operation mode. 6.6.9. AGC_GAIN It is possible to read out the actual setting of AGC_GAIN in Automatic Gain Mode. In standard applications, this register is not of interest for the customer. AGC_GAIN max. amplification (20 dB) min. amplification (3 dB) 0021Ehex 0001 0100 0000 0000 14hex 00hex 32 Micronas PRELIMINARY DATA SHEET MSP 34x5D Table 6-15: Sequences to initialize and start the MSP 34x5D LOAD_SEQ_1/2: General Initialization General Programming Mode Write into MSP 34x5D: 1. AD_CV 2. FIR1 3. FIR2 4. MODE_REG 5. DCO1_LO 6. DCO1_HI 7. DCO2_LO 8. DCO2_HI AUDIO PROCESSING INIT Initialization of Audio Baseband Processing section, which may be customer dependant (see section 7.). NICAM_WAIT: Automatic Start of the NICAM-Decoder if Bit[6] of MODE_REG is set to 1 1. Wait at least 0.25 s NICAM_CHECK: Read NICAM specific information and check for presence, operation mode, and quality of NICAM signal. DO NOT read and DO NOT evaluate Stereo Detection register. Read out of MSP 34x5D (For MSP 3405D, all NICAM read registers contain "0"): 1. C_AD_BITS 2. CONC_CT or ERROR_RATE; if AUTO_FM is active, reading of CONC_CT or ERROR_RATE can be omitted. Evaluation of C_AD_BITS and CONC_CT or ERROR_RATE in the CCU (see section 6.6.). If necessary, switch the corresponding sound channels within the audio baseband processing section. FM_WAIT: Automatic start of the FM-identification process if Bit[6] of MODE_REG is set to 0. 1. Ident Reset 2. Wait at least 0.5 s FM_IDENT_CHECK: Read Stereo Detection register and check for operation mode of dual carrier FM. DO NOT read and DO NOT evaluate NICAM specific information. Read out of MSP 34x5D: 1. Stereo Detection register (DSP register 0018hex, high part) Evaluation of the Stereo Detection register (see section 7.5.1.) If necessary, switch the corresponding sound channels within the audio baseband processing section. LOAD_SEQ_1: Reinitialization of Channel 1 without affecting Channel 2 Write into MSP 34x5D: 1. FIR1 2. MODE_REG 3. DCO1_LO 4. DCO1_HI (6 8 bit) (12 bit) (12 bit) Write into MSP 34x5D: For example: Addr: 0020hex, Data: 0003hex Demodulator Short Programming Write into MSP 34x5D: For example: Addr: 0020hex, Data 0008hex Alternatively, for terrestrial reception, the autodetect feature can be applied. PAUSE: Duration of "Pause" determines the repetition rate of the NICAM or the FM_IDENT-check. Micronas 33 MSP 34x5D 6.8. Software Proposals for Multistandard TV-Sets To familiarize the reader with the programming scheme of the MSP 34x5D demodulator part, three examples in the shape of flow diagrams are shown in the following sections. PRELIMINARY DATA SHEET 6.8.2. Multistandard Including System B/G with NICAM/FM-Mono and German DUAL FM Fig. 6-3 shows a flow diagram for the CCU software, applied for the MSP 34x5D in a TV set, which supports all standards according to System B/G. For the instructions used in the diagram, please refer to Table 6-15. After having switched on the TV-set and having initialized the MSP 34x5D (LOAD_SEQ_1/2), FM-mono sound is available. Fig. 6-3 shows that to check for any stereo or bilingual audio information, the sound standards 0008hex (B/GNICAM) and 0003hex must simply be set alternately. If successful, the MSP 3415D must switch to the desired audio mode. 6.8.1. Multistandard Including System B/G or I (NICAM/FM-Mono only) or SECAM L (NICAM/AM-Mono only) Fig. 6-1 shows a flow diagram for the CCU software, applied for the MSP 34x5D in a TV set, which facilitates NICAM and FM/AM-mono sound. For the instructions, please refer to Table 6-15. If the program is changed, resulting in another program within the same TV-sound system, no parameters of the MSP 34x5D need be modified. To facilitate the check for NICAM, the CCU has only to continue at the 'NICAM_WAIT' instruction. During the NICAM-identification process, the MSP 34x5D must be switched to the FM-mono sound. 6.8.3. Satellite Mode Fig. 6-2 shows the simple flow diagram to be used for the MSP 34x5D in a satellite receiver. For FM-mono operation, the corresponding FM carrier should preferably be processed at the MSP-channel 2. START START LOAD_SEQ_1/2 Set Sound Standard 0008hex Alternatively: 0009hex 000Ahex MSP-Channel 1 FM2-Parameter MSP-Channel 2 FM1-Parameter Audio Processing Init Audio Processing Init STOP NICAM_WAIT Fig. 6-2: CCU software flow diagram: SAT-mode 6.8.4. Automatic Search Function for FM-Carrier Detection Pause NICAM_CHECK Fig. 6-1: CCU software flow diagram for NICAM/FM or AM mono with Demodulator Short Programming The AM demodulation ability of the MSP 34x5D offers the possibility to calculate the "field strength" of the momentarily selected FM carrier, which can be read out by the CCU. In SAT receivers, this feature can be used to make automatic FM carrier search possible. Therefore, the MSPD has to be switched to AM-mode (MODE_REG[8]), FM-Prescale must be set to 7Fhex = +127dec, and the FM DC notch must be switched off. The sound-IF frequency range must now be "scanned" in the MSPD-channel 2 by means of the programmable quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz). 34 Micronas PRELIMINARY DATA SHEET MSP 34x5D After each incrementation, a field strength value is available at the quasi-peak detector output (quasi-peak detector source must be set to FM), which must be examined for relative maxima by the CCU. This results in either continuing search or switching the MSP 34x5D back to FM demodulation mode. During the search process, the FIR2 must be loaded with the coefficient set "AUTOSEARCH", which enables small bandwidth, resulting in appropriate field strength characteristics. The absolute field strength value (can be read out of "quasi peak detector output FM1") also gives information on whether a main FM carrier or a subcarrier was detected, and as a practical consequence, the FM bandwidth (FIR1/2) and the deemphasis (50 s or adaptive) can be switched automatically. Due to the fact that a constant demodulation frequency offset of a few kHz, leads to a DC-level in the demodulated signal, further fine tuning of the found carrier can be achieved by evaluating the "DC Level Readout FM1". Therefore, the FM DC Notch must be switched on, and the demodulator part must be switched back to FM-demodulation mode. For a detailed description of the automatic search function, please refer to the corresponding MSP 3400C Windows software. Note: The automatic search is still possible by evaluating only the DC Level Readout FM1 (DC Notch On) as it is described with the MSP 3410B, but the above mentioned method is faster. If this DC Level method is applied with the MSP 34x5D, it is recommended to set MODE_REG[15] to 1 (AM-Gain= 12 dB) and to use the new Autosearch FIR2 coefficient set as given in Table 6-11. START LOAD_SEQ_1/2 Set Sound Standard 0008hex Audio Processing Init NICAM_WAIT Pause Yes NICAM_CHECK NICAM ? No LOAD_SEQ_1 Set Sound Standard 0003hex FM_WAIT Pause FM_ IDENT_CHECK Stereo/Biling. Mono LOAD_SEQ_1 Set Sound Standard 0008hex Fig. 6-3: CCU software flow diagram: standard B/G with NICAM or FM stereo with Demodulator Short Programming Mode Micronas 35 MSP 34x5D 7. Programming the DSP Section (Audio Baseband Processing) 7.1. DSP Write Registers: Table and Addresses PRELIMINARY DATA SHEET Table 7-1: DSP Write Registers; Subaddress: 12hex; if necessary these registers are readable as well. DSP Write Register Volume loudspeaker channel Volume / Mode loudspeaker channel Balance loudspeaker channel [L/R] Balance Mode loudspeaker Bass loudspeaker channel Treble loudspeaker channel Loudness loudspeaker channel Loudness Filter Characteristic Spatial effect strength loudspeaker ch. Spatial effect mode/customize Volume SCART1 channel Volume / Mode SCART1 channel Loudspeaker channel source Loudspeaker channel matrix SCART1 channel source SCART1 channel matrix I2S channel source 000Bhex 000Ahex 0008hex 0007hex 0005hex 0002hex 0003hex 0004hex 0001hex Address 0000hex High/ Low H L H L H H H L H L H L H L H L H L Adjustable Range, Operational Modes [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control [0..100 / 100 % and vv][-127..0 / 0 dB and vv] [Linear mode / logarithmic mode] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [-100%...OFF...+100%] [SBE, SBE+PSE] [00hex ... 7Fhex],[+12 dB ... -114 dB, MUTE] [Linear mode / logarithmic mode] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO] [FM/AM, NICAM, SCART, I2S1, I2S2] Reset Mode MUTE 00hex 100%/100% linear mode 0 dB 0 dB 0 dB NORMAL OFF SBE+PSE 00hex linear mode FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM /AM EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E EE E EEEEEE E EE E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EE E Quasi-peak detector source Quasi-peak detector matrix Prescale SCART Prescale FM/AM FM matrix Deemphasis FM Adaptive Deemphasis FM Prescale NICAM (MSP 3415D only) Prescale I2S2 ACB Register (SCART Switching Facilities) Beeper Identification Mode Prescale I2S1 FM DC Notch Automatic Volume Correction 0010hex 0012hex 0013hex 0014hex 0015hex 0016hex 0017hex 0029hex 000Fhex 000Chex H L [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO] [00hex ... 7Fhex] [00hex ... 7Fhex] [NO_MAT, GSTEREO, KSTEREO] [OFF, 50 s, 75 s, J17] [OFF, WP1] [00hex ... 7Fhex] [00hex ... 7Fhex] Bits [15..0] [00hex ... 7Fhex]/[00hex ... 7Fhex] [B/G, M] [00hex ... 7Fhex] [ON, OFF] [off, on, decay time] SOUNDA 00hex 00hex NO_MAT 50 s OFF 00hex 10hex 00hex 0/0 B/G 10hex ON OFF 000Dhex 000Ehex H H L H L H H H/L H/L L H L H I2S channel matrix [SOUNDA, SOUNDB, STEREO, MONO] 36 Micronas PRELIMINARY DATA SHEET MSP 34x5D 7.2. DSP Read Registers: Table and Addresses Table 7-2: DSP Read Registers; Subaddress: 13hex; these registers are not writable DSP Read Register Stereo detection register Quasi peak readout left Quasi peak readout right DC level readout FM1/Ch2-L DC level readout FM2/Ch1-R MSP hardware version code MSP major revision code MSP product code MSP ROM version code Address 0018hex 0019hex 001Ahex 001Bhex 001Chex 001Ehex 001Ehex 001Fhex 001Fhex High/Low H H&L H&L H&L H&L H L H L Output Range [80hex ... 7Fhex] [00hex ... 7FFFhex] [00hex ... 7FFFhex] [8000hex ... 7FFFhex] [8000hex ... 7FFFhex] [00hex ... FFhex] [00hex ... FFhex] [05hex , 0Fhex] [00hex ... FFhex] 8 bit two's complement 16 bit two's complement 16 bit two's complement 16 bit two's complement 16 bit two's complement Micronas 37 MSP 34x5D 7.3. DSP Write Registers: Functions and Values Write registers are 16 bit wide, whereby the MSB is denoted bit [15]. Transmissions via I2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low [7..0] and high [15..8] byte, or in an other manner, thus holding two different control entities. All write registers are readable. Unused parts of the 16-bit registers must be zero. Addresses not given in this table must not be written at any time! 7.3.1. Volume Loudspeaker Channel Volume Loudspeaker +12 dB +11.875 dB +0.125 dB 0 dB -0.125 dB -113.875 dB -114 dB Mute Fast Mute 0000hex 0111 1111 0000 0111 1110 1110 [15..4] 7F0hex 7EEhex PRELIMINARY DATA SHEET Clipping Mode Loudspeaker Reduce Volume Reduce Tone Control Compromise Mode 0000hex 0000 RESET 0001 0010 [3..0] 0hex 1hex 2hex If the clipping mode is set to "Reduce Volume", the following clipping procedure is used: To prevent severe clipping effects with bass or treble boosts, the internal volume is automatically limited to a level where, in combination with either bass or treble setting, the amplification does not exceed 12 dB. If the clipping mode is "Reduce Tone Control", the bass or treble value is reduced if amplification exceeds 12 dB. If the clipping mode is "Compromise Mode", the bass or treble value and volume are reduced half and half if amplification exceeds 12 dB. 0111 0011 0010 732hex 0111 0011 0000 730hex 0111 0010 1110 72Ehex 0000 0001 0010 012hex 0000 0001 0000 010hex 0000 0000 0000 000hex RESET 1111 1111 1110 FFEhex Example: Red. Volume Red. Tone Con. Compromise Vol.: +6 dB 3 6 4.5 Bass: +9 dB 9 6 7.5 Treble: +5 dB 5 5 5 The highest given positive 8-bit number (7Fhex) yields in a maximum possible gain of 12 dB. Decreasing the volume register by 1 LSB decreases the volume by 1 dB. Volume settings lower than the given minimum mute the output. With large scale input signals, positive volume settings may lead to signal clipping. The MSP 34x5D loudspeaker volume function is divided up in a digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. Going back from Fast Mute should be done to the volume step before Fast Mute was activated. The Fast Mute facility is activated by the I2C command. After 75 ms (typically), the signal is completely ramped down. 38 Micronas PRELIMINARY DATA SHEET MSP 34x5D 7.3.3. Bass Loudspeaker Channel Bass Loudspeaker +20 dB +18 dB +16 dB +14 dB 0002hex 0111 1111 0111 1000 0111 0000 0110 1000 0110 0000 0101 1000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H 7Fhex 78hex 70hex 68hex 60hex 58hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex 7.3.2. Balance Loudspeaker Channel Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. In linear mode, a step by 1 LSB decreases or increases the balance by about 0.8% (exact figure: 100/127). In logarithmic mode, a step by 1 LSB decreases or increases the balance by 1 dB. Balance Mode Loudspeaker linear logarithmic 0001hex 0000 RESET 0001 [3..0] 0hex 1hex +12 dB +11 dB +1 dB +1/8 dB Linear Mode Balance Loudspeaker Channel [L/R] Left muted, Right 100% Left 0.8%, Right 100% Left 99.2%, Right 100% Left 100%, Right 100% Left 100%, Right 99.2% Left 100%, Right 0.8% Left 100%, Right muted 0001hex 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0010 1000 0001 H 7Fhex 7Ehex 01hex 00hex FFhex 82hex 81hex 0 dB -1/8 dB -1 dB -11 dB -12 dB With positive bass settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. Logarithmic Mode Balance Loudspeaker Channel [L/R] Left -127 dB, Right 0 dB Left -126 dB, Right 0 dB Left -1 dB, Right 0 dB Left 0 dB, Right 0 dB Left 0 dB, Right -1 dB Left 0 dB, Right -127 dB Left 0 dB, Right -128 dB 0001hex 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0001 1000 0000 H 7Fhex 7Ehex 01hex 00hex FFhex 81hex 80hex Micronas 39 MSP 34x5D 7.3.4. Treble Loudspeaker Channel Treble Loudspeaker +15 dB +14 dB +1 dB +1/8 dB 0 dB -1/8 dB -1 dB -11 dB -12 dB 0003hex 0111 1000 0111 0000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H 78hex 70hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex Enlargement 1.5% Effect off With positive treble settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. Reduction 1.5% Reduction 50% Reduction 100% 7.3.5. Loudness Loudspeaker Channel Loudness Loudspeaker +17 dB +16 dB +1 dB 0 dB 0004hex 0100 0100 0100 0000 0000 0100 0000 0000 RESET H 44hex 40hex 04hex 00hex Spatial Effect Mode Loudspeaker Stereo Basewidth Enlargement (SBE) and Pseudo Stereo Effect (PSE). (Mode A) PRELIMINARY DATA SHEET to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. By means of `Mode Loudness', the corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz. 7.3.6. Spatial Effects Loudspeaker Channel Spatial Effect Strength Loudspeaker Enlargement 100% Enlargement 50% 0005hex 0111 1111 0011 1111 0000 0001 0000 0000 RESET 1111 1111 1100 0000 1000 0000 H 7Fhex 3Fhex 01hex 00hex FFhex C0hex 80hex 0005hex 0000 RESET 0000 0010 [7:4] 0hex 0hex 2hex Stereo Basewidth Enlargement (SBE) only. (Mode B) Mode Loudness Loudspeaker Normal (constant volume at 1 kHz) Super Bass (constant volume at 2 kHz) 0004hex 0000 0000 RESET 0000 0100 L 00hex 04hex Spatial Effect Customize Coefficient Loudspeaker max high pass gain 2/3 high pass gain 1/3 high pass gain min high pass gain 0005hex [3:0] 0000 RESET 0010 0100 0110 1000 0hex 2hex 4hex 6hex 8hex Loudness increases the volume of low and high frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended 40 automatic Micronas PRELIMINARY DATA SHEET MSP 34x5D There are several spatial effect modes available: Mode A (low byte = 00hex) is compatible to the formerly used spatial effect. Here, the kind of spatial effect depends on the source mode. If the incoming signal is in mono mode, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A rather strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode A, even in case of stereo input signals, Pseudo Stereo Effect is active, which reduces the center image. In Mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on. It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0000bin yields a flat response for center signals (L = R) but a high pass function of L or R only signals. A value of 0110bin has a flat response for L or R only signals but a lowpass function for center signals. By using 1000bin, the frequency response is automatically adapted to the sound material by choosing an optimal high pass gain. Logarithmic Mode Volume SCART1 +12 dB +11.875 dB +0.125 dB 0 dB -0.125 dB -113.875 dB -114 dB Mute 0007hex 0111 1111 0000 0111 1110 1110 [15..4] 7F0hex 7EEhex 0111 0011 0010 732hex 0111 0011 0000 730hex 0111 0010 1110 72Ehex 0000 0001 0010 012hex 0000 0001 0000 010hex 0000 0000 0000 000hex RESET 7.3.8. Channel Source Modes Loudspeaker Source SCART1 Source I2S Source Quasi-Peak Detector Source FM/AM 0008hex 000Ahex 000Bhex 000Chex 0000 0000 RESET 0000 0001 0000 0010 0000 0101 0000 0110 H H H H 00hex 01hex 02hex 05hex 06hex 7.3.7. Volume SCART1 NICAM (MSP 3415D only) Volume Mode SCART1 linear logarithmic 0007hex 0000 RESET 0001 [3..0] SCART 0hex 1hex I2S1 I2S2 7.3.9. Channel Matrix Modes Linear Mode Volume SCART1 OFF 0 dB gain (digital full scale (FS) to 2 VRMS output) +6 dB gain (-6 dBFS to 2 VRMS output) 0007hex 0000 0000 RESET 0100 0000 H 00hex 40hex Loudspeaker Matrix SCART1 Matrix I2S Matrix Quasi-Peak Detector Matrix SOUNDA / LEFT / MSP-IF-CHANNEL2 0111 1111 7Fhex SOUNDB / RIGHT / MSP-IF-CHANNEL1 STEREO MONO 0008hex 000Ahex 000Bhex 000Chex 0000 0000 RESET 0001 0000 0010 0000 0011 0000 L L L L 00hex 10hex 20hex 30hex Micronas 41 MSP 34x5D 7.3.10. SCART Prescale Volume Prescale SCART OFF 0 dB gain (2 VRMS input to digital full scale) +14 dB gain (400 mVRMS input to digital full scale) 000Dhex 0000 0000 RESET 0001 1001 0111 1111 H 00hex 19hex 7Fhex PRELIMINARY DATA SHEET 7.3.11. FM/AM Prescale Volume Prescale FM (Normal FM Mode) OFF Maximum Volume (28 kHz deviation 1) recommended FIRbandwidth: 130 kHz) Deviation 50 kHz1) recommended FIRbandwidth: 200 kHz Deviation 75 kHz1) recommended FIRbandwidth: 200 or 280 kHz Deviation 150 kHz1) recommended FIRbandwidth: 380 kHz Maximum deviation 192 kHz1) recommended FIRbandwidth: 380 kHz Prescale for adaptive deemphasis WP1 recommended FIRbandwidth: 130 kHz Volume Prescale FM (High Dev.- Mode) OFF Deviation 150 kHz1) recommended FIRbandwidth: 380 kHz Maximum deviation 384 kHz1) recommended FIRbandwidth: 500 kHz Volume Prescale AM OFF SIF input level: 0.1 Vpp - 0.8 Vpp 1) 2) 0.8 Vpp - 1.4 Vpp 1) 0111 1100 7Chex <7Chex 000Ehex 0000 0000 RESET 0111 1111 H 00hex 7Fhex 0100 1000 48hex Comments for the FM/AM-Prescaling: For the High Deviation Mode, the FM prescaling values can be used in the range from 13hex to 30hex. Please consider the internal reduction of 6 dB for this mode. The FIR-bandwidth should be selected to 500 kHz. deviations will result in internal digital full scale signals. Appropriate clipping headroom has to be set by the customer. This can be done by decreasing the listed values by a specific factor. 2) In the mentioned SIF-level range, the AM-output level 1) Given 0011 0000 30hex 0001 1000 18hex 0001 0011 13hex remains stable and independent of the actual SIF-level. In this case, only the AM degree of audio signals above 40 Hz determines the AM-output level. 0001 0000 10hex 000Ehex 0000 0000 RESET 0011 0000 H 00hex 30hex 0001 0100 14hex 000Ehex 0000 0000 RESET H 00hex Note: For AM, the bit MODE_REG[15] must be 1. 42 Micronas PRELIMINARY DATA SHEET MSP 34x5D 7.3.17. I2S1 and I2S2 Prescale 000Ehex 0000 0000 RESET 0000 0001 0000 0010 L 00hex 01hex 02hex +18 dB gain Prescale I2S1 Prescale I2S2 OFF 0016hex 0012hex 0000 0000 0001 0000 RESET 0111 1111 H H 00hex 10hex 7Fhex 7.3.12. FM Matrix Modes FM Matrix NO MATRIX GSTEREO KSTEREO 0 dB gain NO_MATRIX is used for terrestrial mono or satellite stereo sound. GSTEREO dematrixes [(L+R)/2, R] to [L, R] and is used for German dual carrier stereo system (Standard B/G). KSTEREO dematrixes [(L+R)/2, (L-R)/2] to [L, R] and is used for the Korean dual carrier stereo system (Standard M). 7.3.13. FM Fixed Deemphasis Deemphasis FM 50 s 75 s J17 OFF 000Fhex 0000 0000 RESET 0000 0001 0000 0100 0011 1111 H 00hex 01hex 04hex 3Fhex 7.3.18. ACB Register (see Fig. 4-3); [15:14] = 0 ! Definition of Digital Control Output Pins ACB Register D_CTR_OUT0 low (RESET) high D_CTR_OUT1 low (RESET) high 0013hex x0 x1 0x 1x [15..14] 7.3.14. FM Adaptive Deemphasis FM Adaptive Deemphasis WP1 OFF WP1 000Fhex 0000 0000 RESET 0011 1111 L 00hex 3Fhex Definition of SCART Switching Facilities ACB Register DSP IN Selection of Source: * SC1_IN_L/R MONO_IN SC2_IN_L/R Mute SC1_OUT_L/R Selection of Source: SC2_IN_L/R MONO_IN SCART1 via D/A SC1_IN_L/R Mute 0013hex [13..0] xx xx xx xx xx00 xx01 xx10 xx11 xx00 xx00 xx00 xx10 0000 0000 0000 0000 7.3.15. NICAM Prescale (MSP 3415D only) Volume Prescale NICAM OFF 0 dB gain +12 dB gain 0010hex 0000 0000 RESET 0010 0000 0111 1111 H 00hex 20hex 7Fhex xx xx xx xx xx 01xx 10xx 11xx 01xx 11xx x0x0 x0x0 x0x0 x1x0 x1x0 0000 0000 0000 0000 0000 * = RESET position, which becomes active at the time of the first write transmission on the control bus to the audio processing part (DSP). By writing to the ACB register first, the RESET state can be redefined. Note: After RESET, SC1_OUT_L/R is undefined! 7.3.16. NICAM Deemphasis (MSP 3415D only) A J17 Deemphasis is always applied to the NICAM signal. It is not switchable. Micronas Note: If "MONO_IN" is selected at the DSP_IN selection, the channel matrix mode of the corresponding output channel(s) must be set to "sound A". 43 MSP 34x5D 7.3.19. Beeper Beeper Volume OFF Maximum Volume (full digital scale FDS) Beeper Frequency 16 Hz (lowest) 1 kHz 4 kHz (highest) 0014hex 0000 0000 RESET 0111 1111 0014hex 0000 0001 0100 0000 1111 1111 H 00hex 7Fhex L 01hex 40hex FFhex 7.3.21. FM DC Notch PRELIMINARY DATA SHEET The DC compensation filter (FM DC Notch) for FM input can be switched off. This is used to speed up the automatic search function (see section 6.8.4.). In normal FMmode, the FM DC Notch should be switched on. FM DC Notch ON OFF 0017hex 0000 0000 Reset 0011 1111 L 00hex 3Fhex 7.3.22. Automatic Volume Correction (AVC) A squarewave beeper can be added to the loudspeaker channel. The addition point is just before volume adjustment. AVC AVC AVC 0015hex 0000 0000 RESET 0000 0001 0011 1111 L 00hex 01hex 3Fhex AVC 8 sec 4 sec 2 sec 20 ms on/off off and Reset of int. variables on Decay Time (long) (middle) (short) (very short)1) 0029hex 0000 RESET 1000 0029hex 1000 0100 0010 0001 [15:12] 0hex 8hex [11:8] 8hex 4hex 2hex 1hex 7.3.20. Identification Mode Identification Mode Standard B/G (German Stereo) Standard M (Korean Stereo) Reset of Ident-Filter 1) intended for quick adaptation to the average volume level after channel change To shorten the response time of the identification algorithm after a program change between two FM-stereo capable programs, the reset of the ident-filter can be applied. Sequence: 1. Program change 2. Reset ident-filter 3. Set identification mode back to standard B/G 4. Wait approx. 0.5 sec. 5. Read stereo detection register Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The AVC solves this problem by equalizing the volume level. To prevent clipping, the AVC's gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low-level inputs. The decay time is programmable by the AVC register bits [11:8]. For input signals ranging from -24 dBr to 0 dBr, the AVC maintains a fixed output level of -18 dBr. Fig. 7-1 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is - SCART in-, output 0 dBr = 2.0 Vrms - Loudspeaker and Aux output 0 dBr = 1.4 Vrms 44 Micronas PRELIMINARY DATA SHEET MSP 34x5D 7.5.1. Stereo Detection Register Stereo Detection Register Stereo/Bilingual Mode 0018hex H output level [dBr] -12 -18 -24 Reading ID-level (two's complement) near zero positive value (ideal reception: 7Fhex) negative value (ideal reception: 80hex) MONO STEREO -30 -24 -18 -12 -6 0 +6 input level [dBr] Fig. 7-1: Simplified AVC characteristics BILINGUAL To reset the internal variables, the AVC should be switched off and on during any channel or source change. For standard applications, the recommended decay time is 4 sec. Note: AVC should not be used in any Dolby Pro Logic mode. If FM Adaptive Deemphasis WP1 is active, the ID-level in Stereo Detection Register is not valid. A control processor evaluating the content of the Stereo Detection Register (ID-level), should use the threshold recommendations, shown in Fig. 7-2 for switching to Stereo/Bilingual and back to Mono mode. Mode Stereo 7.4. Exclusions for the Audio Baseband Features In general, all functions can be switched independently of the others. One exception exists: 1. NICAM cannot be processed simultaneously with the FM2 channel (MSP 3415D only). 2. FM adaptive deemphasis WPI cannot be processed simultaneously with the FM-identification. Fig. 7-2: Recommended thresholds for Stereo/ Mono/Bilingual switching 7.5. DSP Read Registers: Functions and Values All readable registers are 16-bit wide. Transmissions via I2C bus have to take place in 16-bit words. Single data entries are 8 bit. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writeable. 7.5.2. Quasi-Peak Detector Quasi-Peak Readout Left Quasi-Peak Readout Right Quasi peak readout 0019hex 001Ahex H+L H+L -25 -20 Mono 20 25 ID-level [Dec] Biling. [0hex ... 7FFFhex] values are 16 bit two's complement The quasi peak readout register can be used to read out the quasi peak level of any input source, in order to adjust all inputs to the same normal listening level. The refresh rate is 32 kHz. The feature is based on a filter time constant: attack-time: 1.3 ms decay-time: 37 ms Micronas 45 MSP 34x5D 7.5.3. DC Level Register DC Level Readout FM1 (MSP-Ch2) DC Level Readout FM2 (MSP-Ch1) DC Level 001Bhex 001Chex H+L H+L PRELIMINARY DATA SHEET 7.5.5. MSP Major Revision Code Major Revision MSP 34x5D 001Ehex 04hex L [8000hex ... 7FFFhex] values are 16 bit two's complement The MSP 34x5D is the fourth generation of ICs in the MSP family. 7.5.6. MSP Product Code Product MSP 3405D MSP 3415D 001Fhex 05hex 0Fhex H The DC level register measures the DC component of the incoming FM signals (FM1 and FM2). This can be used for seek functions in satellite receivers and for IF FM frequencies fine tuning. A too low demodulation frequency (DCO) results in a positive DC-Level and vice versa. For further processing, the DC content of the demodulated FM signals is suppressed. The time constant , defining the transition time of the DC Level Register, is approximately 28 ms. 7.5.4. MSP Hardware Version Code Hardware Version Hardware Version MSP 34x5D - A2 MSP 34x5D - B3 001Ehex [00hex ... FFhex] 01hex 02hex H By means of the MSP-Product Code, the control processor is able to decide whether or not NICAM-controlling should be accomplished. 7.5.7. MSP ROM Version Code ROM Version Major software revision MSP 34x5D - A2 MSP 34x5D - B3 001Fhex [00hex ... FFhex] 22hex 23hex L A change in the hardware version code defines hardware optimizations that may have influence on the chip's behavior. The readout of this register is identical to the hardware version code in the chip's imprint. A change in the ROM version code defines internal software optimizations, that may have influence on the chip's behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new MSP 34x5D versions according to this number. To avoid compatibility problems with the MSPB series, an offset of 20hex is added to the ROM version code of the chip's imprint. 46 Micronas PRELIMINARY DATA SHEET MSP 34x5D 8. Specifications 8.1. Outline Dimensions 0.9 0.2 16 x 1.27 = 20.32 0.1 1.27 1.2 x 45 1.1 x 45 9 10 2 9 25.14 0.12 0.71 0.05 1 61 60 0.48 0.06 7.5 9 0.23 0.04 7.5 26 27 25.14 0.12 43 44 1.9 0.05 4.05 0.1 4.75 0.15 0.1 24.2 0.1 SPGS0027-2(P68)/1E Fig. 8-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm SPGS0016-5(P64)/1E SPGS0016-5(P52)/1E 64 33 52 27 1 1 32 26 47.0 0.1 57.7 0.1 0.8 0.2 3.8 0.1 19.3 0.1 18 0.05 0.6 0.2 4.0 0.1 15.6 0.1 14 0.1 0.28 0.06 2.8 0.2 0.28 0.06 3.2 0.2 1 0.05 1.778 0.48 0.06 31 x 1.778 = 55.1 0.1 20.3 0.5 1 0.05 1.778 0.48 0.06 25 x 1.778 = 44.4 0.1 16.3 1 Fig. 8-2: 64-Pin Plastic Shrink Dual Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm Fig. 8-3: 52-Pin Plastic Shrink Dual In Line Package (PSDIP52) Weight approximately 5.5 g Dimensions in mm Micronas 16 x 1.27 = 20.32 0.1 2 23.3 0.3 24.2 0.1 1.27 47 MSP 34x5D PRELIMINARY DATA SHEET 0.17 0.04 64 65 1.8 10.3 9.8 16 8 0.37 0.05 14 0.1 41 40 23 x 0.8 = 18.4 0.1 0.8 17.2 0.15 1.8 8 5 80 1 25 1.3 0.05 2.7 0.1 3 0.2 0.1 20 0.1 24 23.2 0.15 Fig. 8-4: 80-Pin Plastic Quad Flat Package (PQFP80) Weight approximately 1.61 g Dimensions in mm SPGS705000-1(P80)/1E 10 x 0.8 = 8 0.1 0.17 0.06 33 34 13.2 0.2 23 22 10 0.1 0.8 0.8 1.3 12 1 1.75 13.2 0.2 2.15 0.2 11 1.75 44 2.0 0.1 0.1 10 0.1 0.375 0.075 Fig. 8-5: 44-Pin Plastic Metric Quad Flat Package (PMQFP44) Weight approx. 0.4 g Dimensions in mm SPGS0006-3(P44)/1E 48 10 x 0.8 = 8 0.1 15 x 0.8 = 12.0 0.1 0.8 Micronas PRELIMINARY DATA SHEET MSP 34x5D 8.2. Pin Connections and Short Descriptions NC = not connected (leave vacant for future compatibility reasons) TP = Test Pin (leave vacant; pin is used for production test only) LV = leave vacant X = obligatory; connect as described in application circuit diagram Pin No. PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PMQFP 44-pin Pin Name Type Connection (if not used) sed) Short Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 - - - 16 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - 1 64 63 62 61 60 59 58 57 - - - 14 - 13 12 11 10 9 8 7 - 6 5 4 3 - - - 2 1 52 51 50 49 48 47 46 - - - 9 - 8 7 6 5 4 3 2 1 80 79 78 77 76 75 - 74 73 72 71 70 69 68 67 66 65 64 63 1) - - - 17 16 15 14 13 12 - 11 10 9 8 - - - - 7 6 5 4 - 3 2 1 - - - TP NC TP I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL NC STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 NC NC NC NC TP XTAL_OUT XTAL_IN TESTEN NC ANA_IN- ANA_IN1+ AVSUP AVSUP NC NC OUT LV LV Test pin Not connected Test pin I2S1 data input I2S data output I2S word strobe I2S clock I2C data I2C clock Not connected Standby (low-active) I2C Bus address select Digital control output 0 Digital control output 1 Not connected Not connected Not connected Not connected Test pin Crystal oscillator Crystal oscillator Test pin Not connected IF common IF input 1 Analog power supply +5 V Analog power supply +5 V Not connected Not connected OUT IN OUT IN/OUT IN/OUT IN/OUT IN/OUT LV LV LV LV LV X X LV IN IN OUT OUT X X LV LV LV LV LV LV LV OUT IN IN X X X LV IN IN LV LV X X LV LV Micronas 49 MSP 34x5D PRELIMINARY DATA SHEET Pin No. PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PMQFP 44-pin Pin Name Type Connection (if not used) Short Description 27 - 28 - 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 - - - 44 45 46 47 48 49 50 51 52 56 - 55 - 54 53 52 51 50 49 48 47 46 45 44 43 - 42 41 - - - 40 39 38 37 36 35 34 33 - 45 - 44 - 43 42 41 - 40 39 - 38 37 - - - - 36 35 - - - 34 33 32 31 30 29 28 27 - 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 1) 44 - 43 - 42 41 40 39 38 37 - - - - - - - 36 35 - - - 34 33 32 31 30 29 28 - - AVSS AVSS MONO_IN NC VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L NC NC NC NC NC NC NC AGNDC AHVSS AHVSS NC NC CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC NC OUT OUT IN IN IN IN IN X X LV LV X LV LV AHVSS LV LV LV or AHVSS LV LV LV LV LV LV X X X LV LV X X LV LV LV X LV LV LV Analog ground Analog ground Mono input Not connected Reference voltage IF A/D converter Scart 1 input, right Scart 1 input, left Analog shield ground 1 Scart 2 input, right Scart 2 input, left Not connected Not connected Not connected Not connected Not connected Not connected Not connected Analog reference voltage high voltage part Analog ground Analog ground Not connected Not connected Volume capacitor MAIN Analog power supply +8 V Not connected Scart 1 output, left Scart 1 output, right Reference ground 1 high voltage part Not connected Not connected Not connected 50 Micronas PRELIMINARY DATA SHEET MSP 34x5D Pin No. PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PMQFP 44-pin Pin Name Type Connection (if not used) Short Description 53 54 55 56 57 58 59 60 - - 61 62 63 64 65 66 - - 67 - - 68 32 31 30 29 28 27 26 25 - - 24 23 22 21 20 19 - - 18 - - 17 - 26 - 25 24 23 22 21 - - 20 - - 19 18 17 - - 16 - - 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 27 26 25 24 23 - - 22 - - - 21 - - 20 19 - - 18 NC NC NC DACM_L DACM_R VREF2 NC NC NC NC RESETQ NC NC NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP DVSUP DVSUP TP_CO OUT IN IN OUT OUT LV LV LV LV LV X LV LV LV LV X LV LV LV LV X X X X X X LV Not connected Not connected Not connected Loudspeaker out, left Loudspeaker out, right Reference ground 2 high voltage part Not connected Not connected Not connected Not connected Power-on-reset Not connected Not connected Not connected I2S2 data input Digital ground Digital ground Digital ground Digital power supply +5 V Digital power supply +5 V Digital power supply +5 V Test pin (Use this pin to define the capacitor size at crystal oscillator.) 1) Note: For PQFP80 package ONLY and for A2 version ONLY, the following pin-allocation is valid: Pin 74 = TP, Pin 52 = ASG2 Micronas 51 MSP 34x5D 8.3. Pin Configurations TP NC TP I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL TP_CO DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ PRELIMINARY DATA SHEET NC STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 NC NC NC NC TP XTAL_OUT XTAL_IN TESTEN NC ANA_IN- ANA_IN1+ AVSUP 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 NC NC VREF2 DACM_R DACM_L NC NC NC NC NC NC VREF1 SC1_OUT_R SC1_OUT_L NC AHVSUP CAPL_M MSP 34x5D 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L NC NC NC NC NC NC NC AHVSS AGNDC Fig. 8-6: 68-pin PLCC package 52 Micronas PRELIMINARY DATA SHEET MSP 34x5D NC NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 TP TP TP_CO DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ NC NC VREF2 DACM_R DACM_L NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 64 63 62 61 60 59 58 57 56 55 54 53 52 TP XTAL_OUT XTAL_IN TESTEN NC ANA_IN- ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L NC NC NC NC NC NC AGNDC AHVSS CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC TP NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 TP TP TP_CO DVSUP DVSS I2S_DA_IN2 NC RESETQ NC NC VREF2 DACM_R DACM_L NC 1 2 3 4 5 6 7 8 9 10 52 51 50 49 48 47 46 45 44 43 XTAL_OUT XTAL_IN TESTEN NC ANA_IN- ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L NC NC AGNDC AHVSS CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC MSP 34x5D 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 MSP 34x5D 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Fig. 8-8: 52-pin PSDIP package Fig. 8-7: 64-pin PSDIP package Micronas 53 MSP 34x5D PRELIMINARY DATA SHEET SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP NC MONO_IN AVSS AVSS NC NC NC NC NC NC NC NC NC AGNDC AHVSS AHVSS NC NC AVSUP AVSUP ANA_IN1+ ANA_IN- NC TESTEN XTAL_IN XTAL_OUT TP NC NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34 CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC NC NC NC NC DACM_L DACM_R VREF2 NC MSP 34x5D 33 32 31 30 29 28 27 26 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 TP TP TP_CO DVSUP DVSUP NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP NC NC NC RESETQ NC NC Fig. 8-9: 80-pin PQFP package 54 Micronas PRELIMINARY DATA SHEET MSP 34x5D NC VREF1 SC1_OUT_R SC1_OUT_L NC AHVSUP DACM_L DACM_R VREF2 NC NC 33 32 31 30 29 28 27 26 25 24 23 CAPL_M AHVSS AGNDC SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS 34 35 36 37 38 39 40 41 42 43 44 1 AVSUP ANA_IN+ ANA_IN- TESTEN XTAL_IN XTAL_OUT TP 2 3 4 5 6 7 8 9 10 11 STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 22 21 20 19 18 RESETQ I2S_DA_IN2 DVSS DVSUP TP_CO I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL MSP 34x5D 17 16 15 14 13 12 Fig. 8-10: 44-pin PMQFP package 8.4. Pin Circuits (pin numbers refer to PLCC68 package) DVSUP P Fig. 8-11: Input Pins 4, 11, 12, 61, and 65 (I2S_DA_IN1, STANDBYQ, ADR_SEL, RESETQ, and I2S_DA_IN2) N GND Fig. 8-13: Input/Output pins 6 and 7 (I2S_WS, I2S_CL) DVSUP P N GND Fig. 8-12: Output pins 5, 13, 14, and 68 (I2S_DA_OUT, D_CTR_OUT0/1, TP_CO) N GND Fig. 8-14: Input/Output Pins 8 and 9 (I2C_DA, I2C_CL) Micronas 55 MSP 34x5D PRELIMINARY DATA SHEET P 125 k 3.75 V 3-30 pF 500 k Fig. 8-19: Pin 42 (AGNDC) N 3-30 pF 0...2 V Fig. 8-15: Input/Output Pins 20 and 21 (XTAL_OUT/IN) Fig. 8-20: Capacitor Pin 44 (CAPL_M) ANA_IN1+ A D 40 pF 80 k ANA_IN- VREFTOP 300 3.75 V Fig. 8-16: Input Pins 24, 25, and 29 (ANA_IN-, ANA_IN1+, VREFTOP) Fig. 8-21: Output Pins 47, 48 (SC1_OUT_L/R) 24 k 3.75 V Fig. 8-17: Input Pin 28 (MONO_IN) AHVSUP 0...1.2 mA 40 k 3.75 V 3.3 k Fig. 8-18: Input Pins 30, 31, 33, and 34 (SC1-2_IN_L/R) Fig. 8-22: Output Pins 56, 57 (DACM_L/R) 56 Micronas PRELIMINARY DATA SHEET MSP 34x5D 8.5. Electrical Characteristics 8.5.1. Absolute Maximum Ratings Symbol TA TS VSUP1 VSUP2 VSUP3 dVSUP23 PTOT Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP and DVSUP Package Power Dissipation PLCC68 without Heat Spreader PSDIP64 without Heat Spreader PSDIP52 without Heat Spreader PMQFP44 without Heat Spreader Input Voltage, all Digital Inputs Input Current, all Digital Pins Input Voltage, all Analog Inputs Input Current, all Analog Inputs Output Current, all SCART Outputs Output Current, all Analog Outputs except SCART Outputs Output Current, other pins connected to capacitors - SCn_IN_s,3) MONO_IN SCn_IN_s,3) MONO_IN SC1_OUT_s DACM_s3) CAPL_M AGNDC Pin Name - - AHVSUP DVSUP AVSUP AVSUP, DVSUP AHVSUP, DVSUP, AVSUP Min. 0 -40 -0.3 -0.3 -0.3 -0.5 Max. 701) 125 9.0 6.0 6.0 0.5 Unit C C V V V V 1200 1300 1200 9101) -0.3 -20 -0.3 -5 4), 5) 4) mW VIdig IIdig VIana IIana IOana IOana ICana 1) 2) 3) 4) 5) VSUP2+0.3 +20 VSUP1+0.3 +5 4), 5) 4) V mA2) V mA2) 4) 4) For PMQFP44 package, max. ambient operating temperature is 65 C. positive value means current flowing into the circuit "n" means "1" or "2", "s" means "L" or "R" The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground. Total chip power dissipation must not exceed absolute maximum rating. Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. Micronas 57 MSP 34x5D 8.5.2. Recommended Operating Conditions (at TA = 0 to 70 C) Symbol VSUP1 VSUP2 VSUP3 VRLH VRHL Parameter First Supply Voltage Second Supply Voltage Third Supply Voltage RESET Input Low-to-High Transition Voltage RESET Input High-to-Low Transition Voltage (see also Fig. 5-3 on page 19) Digital Input Low Voltage Digital Input High Voltage Digital Input Low Voltage Digital Input High Voltage MSP 34x5D version A1, A2 MSP 34x5D version B3 and later STANDBYQ Setup Time before Turn-off of Second Supply Voltage STANDBYQ, DVSUP STANDBYQ 0.8 0.5 1 ADR_SEL 0.8 Pin Name AHVSUP DVSUP AVSUP RESETQ Min. 7.6 4.75 4.75 0.7 0.45 PRELIMINARY DATA SHEET Typ. 8.0 5.0 5.0 Max. 8.71) 5.25 5.25 0.8 0.55 Unit V V V DVSUP DVSUP VDIGIL VDIGIH VDIGIL VDIGIH 0.2 VSUP2 VSUP2 0.2 VSUP2 VSUP2 VSUP2 s tSTBYQ1 I2C-Bus Recommendations VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C 1) I2C-Bus Input Low Voltage I2C-Bus Input High Voltage I2C Start Condition Setup Time I2C Stop Condition Setup Time I2C-Data Setup Time before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C-Bus Frequency I2C_CL, I2C_DA I2C DA 0.6 120 120 55 55 I2C_CL 500 500 0.3 VSUP2 VSUP2 ns ns ns ns ns ns 1.0 MHz For MSP 34x5D-A1 and -A2 versions in PMQFP44 package, only 8.4 V is allowed. 58 Micronas PRELIMINARY DATA SHEET MSP 34x5D Symbol Parameter Pin Name Min. Typ. Max. Unit I2S-Bus Recommendations VI2SIH I2S-Data Input Low Voltage MSP 34x5D version A1, A2 MSP 34x5D version B3 and later I2S-Data Input High Voltage MSP 34x5D version A1, A2 MSP 34x5D version B3 and later I2S-Data Input Setup Time before Rising Edge of Clock I2S-Data Input Hold Time after falling Edge of Clock I2S-Clock Input Frequency when MSP in I2S-Slave Mode I2S-Clock Input Ratio when MSP in I2S-Slave Mode I2S-Word Strobe Input Frequency when MSP in I2S-Slave Mode I2S-Input Low Voltage when MSP in I2S-Slave Mode MSP 34x5D version A1, A2 MSP 34x5D version B3 and later I2S-Input High Voltage when MSP in I2S-Slave Mode MSP 34x5D version A1, A2 MSP 34x5D version B3 and later I2S-Word Strobe Input Setup Time before Rising Edge of Clock when MSP in I2S-Slave Mode I2S-Word Strobe Input Hold Time after falling Edge of Clock when MSP in I2S-Slave Mode I2S_WS I2S_CL I2S_WS 0.25 0.2 VSUP2 VSUP2 I2S_CL 0.9 32.0 I2S_DA_IN1/2 I2S_CL I2S_DA_IN1/2 0.25 0.2 0.75 0.5 20 0 1.024 1.1 kHz VSUP2 VSUP2 VSUP2 VSUP2 ns ns MHz VI2SIL tI2S1 tI2S2 fI2SCL RI2SCL fI2SWS VI2SIDL VI2SIDH 0.75 0.5 60 VSUP2 VSUP2 ns tI2SWS1 tI2SWS2 0 ns Micronas 59 MSP 34x5D PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit General Crystal Recommendations fP RR C0 CL Crystal Parallel Resonance Frequency at 12 pF Load Capacitance Crystal Series Resistance Crystal Shunt (Parallel) Capacitance External Load Capacitance1) XTAL_IN, XTAL_OUT 18.432 8 6.2 PSDIP PLCC P(M)QFP 25 7.0 1.5 3.3 3.3 MHz pF pF pF pF Crystal Recommendations for Master-Slave Applications fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation vs Temp. Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25 C) XTAL_IN, XTAL_OUT -20 -20 19 18.431 +20 +20 24 18.433 ppm ppm fF MHz Crystal Recommendations for FM / NICAM Applications (No Master-Slave Mode possible) fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation vs Temp. Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25 C) XTAL_IN, XTAL_OUT -30 -30 15 18.4305 18.4335 +30 +30 ppm ppm fF MHz Crystal Recommendations for FM Applications (No Master-Slave Mode possible) fTOL DTEM Accuracy of Adjustment Frequency Variation versus Temperature -100 -50 +100 +50 ppm ppm Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF) VXCA 1) External Clock Amplitude XTAL_IN 0.7 Vpp External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are figures based on experience and should serve as "start value". To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Set MODE_REG 0083hex Bit [14]=1. Measure the frequency at pin TP_CO (see pin description in table on page 51). Change the capacitor size until the free running frequency at pin TP_CO matches 6.144000 MHz (=18.432000 MHz / 3) as closely as possible. The higher the capacity, the lower the resulting clock frequency. 60 Micronas PRELIMINARY DATA SHEET MSP 34x5D Symbol Parameter Pin Name Min. Typ. Max. Unit Analog Input and Output Recommendations CAGNDC AGNDC-Filter-Capacitor Ceramic Capacitor in Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA DC-Decoupling Capacitor in front of SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main Volume Capacitor Main Filter Capacitor CAPL_M DACM_s1) -10% 10 1 +10% MONO_IN SC1_OUT_s1) 10 6.0 SCn_IN_s1) AGNDC -20% -20% -20% 3.3 100 330 +20% 2.0 2.0 F nF nF VRMS VRMS k nF F nF Recommendations for Analog Sound IF Input Signal CVREFTOP VREFTOP-Filter-Capacitor Ceramic Capacitor in Parallel FIF_FM VIF_FM VIF_AM RFMNI Analog Input Frequency Range Analog Input Range FM/NICAM Analog Input Range AM/NICAM Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) BG: I: Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) Ratio: FM-Main/FM-Sub Satellite Ratio: FM1/FM2 German FM-System Ratio: Main FM Carrier/ Color Carrier Ratio: Main FM Carrier/ Luma Components Passband Ripple Suppression of Spectrum Above 9.0 MHz Maximum FM-Deviation (apprx.) normal mode high deviation mode ANA_IN1+, ANA_IN- 15 15 - 15 VREFTOP -20% -20% 0 0.1 0.1 -20 -23 -25 0.8 0.45 -7 -10 -11 7 7 - - - - - 2 - 10 100 9 3 0.8 0 0 0 F nF MHz Vpp Vpp dB dB dB dB dB dB dB dB dB dB RAMNI RFM RFM1/FM2 RFC RFV PRIF SUPHF FMMAX 180 360 kHz 1) "n" means "1" or "2", "s" means "L" or "R" Micronas 61 MSP 34x5D 8.5.3. Characteristics PRELIMINARY DATA SHEET at TA = 0 to 70 C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values at TA = 60 C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature MAIN (M) = Loudspeaker Channel Symbol fCLOCK DCLOCK tJITTER VxtalDC tStartup ISUP1A Parameter Clock Input Frequency Clock High to Low Ratio Clock Jitter (Verification not provided in production test) DC-Voltage Oscillator Oscillator Startup Time at VDD Slew-rate of 1 V/1 s First Supply Current (active) Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at -30 dB Pin Name XTAL_IN Min. Typ. 18.432 Max. Unit MHz Test Conditions 45 55 50 % ps 2.5 XTAL_IN, XTAL_OUT AHVSUP 9.6 6.3 3.5 17.1 11.2 5.6 24.6 16.1 7.7 0.4 2 V ms mA mA mA STANDBYQ = low ISUP1S ISUP2A First Supply Current (standby mode) at Tj = 27 C Second Supply Current (active) MSP 34x5D version A1, A2 MSP 34x5D version B3 and later Third Supply Current (active) MSP 34x5D version A1, A2 MSP 34x5D version B3 and later DVSUP 86 50 AVSUP 15 20 95 70 102 85 mA mA ISUP3A 25 35 35 45 mA mA Digital Contol Outputs VDCTROL VDCTROH I2C-Bus VI2COL II2COH tI2COL1 tI2COL2 I2C-Data Output Low Voltage I2C-Data Output High Current I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock I2C_DA, I2C_CL 15 I2C_DA 0.4 1.0 V A ns II2COL = 3 mA VI2COH = 5 V Digital Output Low Voltage Digital Output High Voltage D_CTR_OUT0 D_CTR_OUT1 D CTR OUT1 4.0 0.4 V V IDCTR = 1 mA IDCTR = -1 mA 100 ns fI2C = 1 MHz 62 Micronas PRELIMINARY DATA SHEET MSP 34x5D Symbol I2S-Bus VI2SOL VI2SOH fI2SWS fI2SCL tI2S1/I2S2 tI2S3 tI2S4 tI2S5 tI2S6 Parameter Pin Name Min. Typ. Max. Unit Test Conditions I2S Output Low Voltage I2S Output High Voltage I2S Word Strobe Output Frequency I2S Clock Output Frequency I2S Clock High/Low Ratio I2S Data Setup Time before Rising Edge of Clock I2S Data Hold Time after Falling Edge of Clock I2S Word Strobe Setup Time before Rising Edge of Clock I2S Word Strobe Hold Time after Falling Edge of Clock I2S_WS I2S_CL I2S CL I2S_DA_OUT I2S_WS I2S_CL 0.4 4.0 32.0 1024 0.9 1 1.1 V V kHz kHz II2SOL = 1 mA II2SOH = -1 mA NICAM-PLL closed I2S_CL I2S_DA_OUT 200 ns CL = 30 pF 180 ns I2S_CL I2S_WS 200 ns 180 ns Analog Ground VAGNDC0 RoutAGN AGNDC Open Circuit Voltage AGNDC Output Resistance AGNDC 3.67 70 3.77 125 3.87 180 V k Rload 10 M 3 V VAGNDC 4 V Analog Input Resistance RinSC RinMONO SCART Input Resistance from TA = 0 to 70 C MONO Input Resistance from TA = 0 to 70 C SCn_IN_s1) 25 40 58 k fsignal = 1 kHz, I = 0.05 mA fsignal = 1 kHz, I = 0.1 mA MONO_IN 15 24 35 k Audio Analog-to-Digital-Converter VAICL Effective Analog Input Clipping Level for Analog-to-DigitalConversion SCn_IN_s1), MONO_IN 2.00 2.25 VRMS fsignal = 1 kHz SCART Outputs RoutSC SCART Output Resistance at Tj = 27 C from TA = 0 to 70 C Deviation of DC-Level at SCART Output from AGNDC Voltage Gain from Analog Input to SCART Output Frequency Response from Analog Input to SCART Output, Bandwidth: 0 to 20000 Hz Effective Signal Level at SCARTOutput during full-scale Digital Input Signal from DSP "s" means "L" or "R" SCn_IN_s1) MONO_IN SC1_OUT_s1) SC1_OUT_s1) 200 200 -70 330 460 500 +70 mV fsignal = 1 kHz, I = 0.1 mA dVOUTSC ASCtoSC frSCtoSC -1.0 +0.5 dB fsignal = 1 kHz with resp. to 1 kHz -0.5 +0.5 dB VoutSC SC1_OUT_s1) 1.8 1.9 2.0 VRMS fsignal = 1 kHz 1) "n" means "1", or "2"; Micronas 63 MSP 34x5D PRELIMINARY DATA SHEET Symbol Main Outputs RoutMA Parameter Pin Name Min. Typ. Max. Unit Test Conditions Main Output Resistance at Tj = 27 C from TA = 0 to 70 C DC-Level at Main-Output for Analog Volume at 0 dB for Analog Volume at -30 dB Effective Signal Level at Main-Output during full-scale Digital Input Signal from DSP for Analog Volume at 0 dB DACM_s1) 2.1 2.1 3.3 4.6 5.0 k k fsignal = 1 kHz, I = 0.1 mA VoutDCMA 1.8 2.04 61 1.37 2.28 V mV VRMS fsignal = 1 kHz VoutMA 1.23 1.51 Analog Performance SNR Signal-to-Noise Ratio from Analog Input to SCART Output MONO_IN, SCn_IN_s1) SC1_OUT_s1) 93 96 dB Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz ... 20 kHz THD Total Harmonic Distortion from Analog Input to SCART Output MONO_IN, SCn_IN_s1) SC1_OUT_s1) 0.01 0.03 % Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz ... 20 kHz XTALK Crosstalk Attenuation between left and right channel within SCART Input/Output pair (LR, RL) SCn_IN SC1_OUT1) Input Level = -3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z < 1 k equally weighted 20 Hz ... 20 kHz 80 dB PSRR: rejection of noise on AHVSUP at 1 kHz PSRR AGNDC From Analog Input to SCART Output AGNDC MONO_IN, SCn_IN_s1) SC1_OUT_s1) DACM_s1), SC1_OUT_s1) 73 80 70 dB dB S/NFM FM Input to Main/SCART Output dB THDFM Total Harmonic Distortion and Noise of FM demodulated signal on Main/SCART Outputs DACM_s1), SC1_OUT_s1) 0.1 % 1 FM-carrier 5.5 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS, unweighted 0 to 15 kHz (for S/N); ( ) full input range, FM-Prescale = 46h, Vol = 0 dB Output Level 1 Vrms at DACM_s; SPM = 3 NICAM: -6 dB, 1 kHz, RMS unweighted 0 to 15 kHz, NICAM_Prescale = 7Fh, Vol = 9 dB Output level 1 VRMS at DACM_s; SPM = 8 S/NNICAM Signal-to-Noise Ratio of NICAM Baseband Signal on Main/SCART Outputs DACM_s1), SC1_OUT_s1) 72 dB 1) "n" means "1" or "2"; "s" means "L" or "R" SPM: Short Programming Mode 64 Micronas PRELIMINARY DATA SHEET MSP 34x5D Symbol THDNICAM Parameter Total Harmonic Distortion and Noise of NICAM Baseband Signal on Main/SCART Outputs NICAM: Bit Error Rate Pin Name DACM_s1), SC1_OUT_s1) Min. Typ. Max. 0.1 Unit % Test Conditions 2.12 kHz, modulator input level = 0 dBref SPM = 8 FM and NICAM, norm conditions SIF input range: 0.1-0.8 Vpp; AM= 70%, 1 kHz, RMS unweighted (S/N); 0 to 15 kHz, FM/AM-Prescale FM/AM Prescale = 3Ch , hex Vol = 0 dB Output level: 0.5 VRMS at DACM_s AM + NICAM, norm conditions; SPM = 9 Gain AGC = 20 dB Gain AGC = 3 dB BERNI S/NAM - DACM_s1), SC1_OUT_s1) 1 10-7 Signal-to-Noise Ratio of AM Baseband Signal on Main/SCART Outputs 48 dB THDAM Total Harmonic Distortion and Noise of AM Demodulated Signal on Main/SCART Outputs DACM_s1), SC1_OUT_s1) 0.3 % RIFIN DCVREFTOP DCANA_IN XTALKIF BWIF AGC dVFMOUT dVNICAMOUT Input Impedance ANA_IN1+, ANA_IN- VREFTOP ANA_IN1+, ANA_IN- ANA_IN1+, ANA_IN- ANA IN 1.5 10.5 2.56 1.3 2 14.1 2.66 1.5 2.5 17.6 2.76 1.7 k k V V DC Voltage at VREFTOP DC Voltage on IF inputs Crosstalk Attenuation 3 dB Bandwidth AGC Step Width Tolerance of Output Voltage of FM Demodulated Signal Tolerance of Output Voltage of NICAM Baseband Signal FM Frequency Response on Main/ SCART Outputs, Bandwidth 20 to 15000 Hz NICAM Frequency Response on Main/SCART Outputs, Bandwidth 20 to 15000 Hz FM Channel Separation (Stereo) 40 10 0.85 dB MHz dB +1.5 dB fsignal = 1 MHz Input Level = -2 dBr 2 DACM_s1), SC1_OUT_s1) DACM_s1), SC1_OUT_s1) DACM_s1), SC1_OUT_s1) -1.5 1 FM-carrier, 50 s, 1 kHz 40 kHz deviation; RMS 2.12 kHz, modulator input level = 0 dBref 1 FM-carrier 5.5 MHz, 50 s, modulator input level = -14.6 dBref; RMS Modulator input level = -12 dB dBref; RMS -1.5 +1.5 dB fRFM -1.0 +1.0 dB fRNICAM DACM_s1), SC1_OUT_s1) -1.0 +1.0 dB SEPFM DACM_s1), SC1_OUT_s1) 50 dB 2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS SEPNICAM XTALKFM NICAM Channel Separation (Stereo) FM Crosstalk Attenuation (Dual) DACM_s1), SC1_OUT_s1) DACM_s1), SC1_OUT_s1) 80 dB 80 dB 2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS XTALKNICAM 1) NICAM Crosstalk Attenuation (Dual) DACM_s1), SC1_OUT_s1) 80 dB "n" means "1" or "2"; "s" means "L" or "R" SPM: Short Programming Mode Micronas 65 MSP 34x5D 9. Application Circuit PRELIMINARY DATA SHEET Signal GND C s. section 8.5.2. Tuner 1 IF 1 IN 10 F - + 100 nF 18.432 MHz + +8.0 V 100 nF 3.3 F 56 pF 56 pF + Alternative circuit for ANA_IN1+ for more attenuation of video components: 100 p 56 p 10 F ANA_IN- (59) 24 ANA_IN1+ (58) 25 XTAL_OUT (63) 20 VREFTOP (54) 29 CAPL_M (40) 44 AGNDC (42) 42 XTAL_IN (62) 21 ANA_IN1+ 1K 28 (55) MONO_IN 330 nF DACM_L (29) 56 1 nF DACM_R (28) 57 1 F 1 F 31 (52) SC1_IN_L 330 nF 30 (53) SC1_IN_R 330 nF 32 (51) ASG1 MAIN AHVSS 34 (49) SC2_IN_L 330 nF 33 (50) SC2_IN_R 330 nF MSP 34x5D 5V 11 (7) STANDBYQ SC1_OUT_L (37) 47 100 22 F + 5V DVSS DVSS 8 (10) I2C_DA 9 (9) I2C_CL D_CTR_OUT0 (5) 13 6 (12) I2S_WS 7 (11) I2S_CL 4 (14) I2S_DA_IN1 65 (20) I2S_DA_IN2 5 (13) I2S_DA_OUT 61 (24) RESETQ TESTEN (61) 22 AVSS 45 (39) AHVSUP D_CTR_OUT1 (4) 14 12 (6) ADR_SEL SC1_OUT_R (36) 48 100 22 F + 67 (18) DVSUP 43 (41) AHVSS 26 (57) AVSUP 49 (35) VREF1 100 nF ResetQ (from CCU, see section.5.3.) 100 nF AVSS 100 nF 5V 5V 8.0 V Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package. 66 Micronas 58 (27) VREF2 66 (19) DVSS 27 (56) AVSS PRELIMINARY DATA SHEET MSP 34x5D 10. Appendix A: MSP 34x5D Version History A1 First hardware release MSP 3415D A2 Second hardware release MSP 3405D and MSP 3415D B3 - I2S Bus supported with version B3 and later versions - digital input specification changed with version B3 and later versions (see section ... ) - max. analog high supply voltage AHVSUP 8.7 V Micronas 67 MSP 34x5D 11. Data Sheet History 1. Preliminary Data Sheet: "MSP 34x5D Multistandard Sound Processors", Aug. 5, 1998, 6251-475-1PD. First release of the preliminary data sheet. 2. Preliminary Data Sheet: "MSP 34x5D Multistandard Sound Processors", Oct. 14, 1999, 6251-475-2PD. Second release of the preliminary data sheet. Major changes: - specification for version B3 added (see Appendix A: Version History) - specification for I2S interface added - section 8.1.: Outline Dimensions for all packages changed PRELIMINARY DATA SHEET Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-475-2PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 68 Micronas |
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